e52738b428
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/pi/agesawrapper.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x01, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x02, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x03, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x05, 0)
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}
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = NULL,
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};
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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VOID
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OemCustomizeInitEarly (
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IN OUT AMD_EARLY_PARAMS *InitEarly
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)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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}
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