439 lines
15 KiB
C
439 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef REG_SCRIPT_H
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#define REG_SCRIPT_H
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci_type.h>
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#include <device/resource.h>
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/*
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* The reg script library is a way to provide data-driven I/O accesses for
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* initializing devices. It currently supports PCI, legacy I/O,
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* memory-mapped I/O, and IOSF accesses.
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*
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* In order to simplify things for the developer the following features
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* are employed:
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* - Chaining of tables that allow runtime tables to chain to compile-time
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* tables.
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*
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* Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
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* and pop of the context. A chained reg_script inherits the previous
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* context (such as current device), but it does not impact the previous
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* context in any way.
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*/
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enum {
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REG_SCRIPT_COMMAND_READ,
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REG_SCRIPT_COMMAND_WRITE,
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REG_SCRIPT_COMMAND_RMW,
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REG_SCRIPT_COMMAND_RXW,
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REG_SCRIPT_COMMAND_POLL,
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REG_SCRIPT_COMMAND_SET_DEV,
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REG_SCRIPT_COMMAND_NEXT,
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REG_SCRIPT_COMMAND_DISPLAY,
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/* Insert new types above this comment */
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REG_SCRIPT_COMMAND_END,
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};
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enum {
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REG_SCRIPT_TYPE_PCI,
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REG_SCRIPT_TYPE_IO,
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REG_SCRIPT_TYPE_MMIO,
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REG_SCRIPT_TYPE_RES,
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REG_SCRIPT_TYPE_IOSF,
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REG_SCRIPT_TYPE_MSR,
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/* Insert other platform independent values above this comment */
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REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000,
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REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE,
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REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000
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};
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enum {
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REG_SCRIPT_SIZE_8,
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REG_SCRIPT_SIZE_16,
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REG_SCRIPT_SIZE_32,
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REG_SCRIPT_SIZE_64,
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};
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struct reg_script {
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uint32_t command;
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uint32_t type;
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uint32_t size;
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uint32_t reg;
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uint64_t mask;
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uint64_t value;
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uint32_t timeout;
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union {
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uint32_t id;
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const struct reg_script *next;
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev;
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#else
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struct device *dev;
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#endif
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unsigned int res_index;
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};
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};
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struct reg_script_context {
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev;
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#else
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struct device *dev;
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#endif
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struct resource *res;
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const struct reg_script *step;
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uint8_t display_state; /* Only modified by reg_script_run_step */
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uint8_t display_features; /* Step routine modifies to control display */
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const char *display_prefix; /* Prefix tag to display */
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};
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struct reg_script_bus_entry {
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uint32_t type;
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uint64_t (*reg_script_read)(struct reg_script_context *ctx);
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void (*reg_script_write)(struct reg_script_context *ctx);
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};
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#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__((used, section(".rsbe_init")))
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#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \
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const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \
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REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_;
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/* Internal helper Macros. */
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#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
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mask_, value_, timeout_, id_) \
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{ .command = cmd_, \
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.type = type_, \
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.size = size_, \
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.reg = reg_, \
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.mask = mask_, \
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.value = value_, \
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.timeout = timeout_, \
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.id = id_, \
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}
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#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
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mask_, value_, timeout_) \
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{ .command = cmd_, \
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.type = type_, \
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.size = size_, \
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.reg = reg_, \
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.mask = mask_, \
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.value = value_, \
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.timeout = timeout_, \
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.res_index = res_index_, \
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}
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/* Display control */
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#define REG_SCRIPT_DISPLAY_ALL 0xff
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#define REG_SCRIPT_DISPLAY_REGISTER 0x02
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#define REG_SCRIPT_DISPLAY_VALUE 0x01
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#define REG_SCRIPT_DISPLAY_NOTHING 0
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#define REG_SCRIPT_DISPLAY_OFF \
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{ .command = REG_SCRIPT_COMMAND_DISPLAY, \
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.value = REG_SCRIPT_DISPLAY_NOTHING, \
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}
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#define REG_SCRIPT_DISPLAY_ON \
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{ .command = REG_SCRIPT_COMMAND_DISPLAY, \
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.value = REG_SCRIPT_DISPLAY_ALL, \
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}
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/*
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* PCI
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*/
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#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_PCI, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_PCI_READ8(reg_) \
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REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
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#define REG_PCI_READ16(reg_) \
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REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
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#define REG_PCI_READ32(reg_) \
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REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
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#define REG_PCI_WRITE8(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
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#define REG_PCI_WRITE16(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
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#define REG_PCI_WRITE32(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
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#define REG_PCI_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
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#define REG_PCI_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
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#define REG_PCI_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
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#define REG_PCI_RXW8(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0)
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#define REG_PCI_RXW16(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0)
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#define REG_PCI_RXW32(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0)
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#define REG_PCI_OR8(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
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#define REG_PCI_OR16(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
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#define REG_PCI_OR32(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
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#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
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#define REG_PCI_XOR8(reg_, value_) \
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REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0)
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#define REG_PCI_XOR16(reg_, value_) \
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REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0)
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#define REG_PCI_XOR32(reg_, value_) \
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REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0)
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/*
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* Legacy IO
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*/
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#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_IO, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_IO_READ8(reg_) \
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REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
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#define REG_IO_READ16(reg_) \
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REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
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#define REG_IO_READ32(reg_) \
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REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
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#define REG_IO_WRITE8(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
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#define REG_IO_WRITE16(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
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#define REG_IO_WRITE32(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
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#define REG_IO_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
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#define REG_IO_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
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#define REG_IO_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
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#define REG_IO_RXW8(reg_, mask_, value_) \
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REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0)
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#define REG_IO_RXW16(reg_, mask_, value_) \
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REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0)
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#define REG_IO_RXW32(reg_, mask_, value_) \
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REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0)
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#define REG_IO_OR8(reg_, value_) \
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REG_IO_RMW8(reg_, 0xff, value_)
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#define REG_IO_OR16(reg_, value_) \
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REG_IO_RMW16(reg_, 0xffff, value_)
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#define REG_IO_OR32(reg_, value_) \
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REG_IO_RMW32(reg_, 0xffffffff, value_)
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#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
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#define REG_IO_XOR8(reg_, value_) \
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REG_IO_RXW8(reg_, 0xff, value_)
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#define REG_IO_XOR16(reg_, value_) \
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REG_IO_RXW16(reg_, 0xffff, value_)
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#define REG_IO_XOR32(reg_, value_) \
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REG_IO_RXW32(reg_, 0xffffffff, value_)
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/*
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* Memory Mapped IO
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*/
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#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_MMIO, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_MMIO_READ8(reg_) \
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REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
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#define REG_MMIO_READ16(reg_) \
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REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
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#define REG_MMIO_READ32(reg_) \
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REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
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#define REG_MMIO_WRITE8(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
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#define REG_MMIO_WRITE16(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
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#define REG_MMIO_WRITE32(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
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#define REG_MMIO_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
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#define REG_MMIO_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
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#define REG_MMIO_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
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#define REG_MMIO_RXW8(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0)
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#define REG_MMIO_RXW16(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0)
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#define REG_MMIO_RXW32(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0)
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#define REG_MMIO_OR8(reg_, value_) \
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REG_MMIO_RMW8(reg_, 0xff, value_)
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#define REG_MMIO_OR16(reg_, value_) \
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REG_MMIO_RMW16(reg_, 0xffff, value_)
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#define REG_MMIO_OR32(reg_, value_) \
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REG_MMIO_RMW32(reg_, 0xffffffff, value_)
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#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
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#define REG_MMIO_XOR8(reg_, value_) \
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REG_MMIO_RXW8(reg_, 0xff, value_)
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#define REG_MMIO_XOR16(reg_, value_) \
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REG_MMIO_RXW16(reg_, 0xffff, value_)
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#define REG_MMIO_XOR32(reg_, value_) \
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REG_MMIO_RXW32(reg_, 0xffffffff, value_)
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/*
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* Access through a device's resource such as a Base Address Register (BAR)
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*/
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#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_RES, bar_, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_)
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#define REG_RES_READ8(bar_, reg_) \
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REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
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#define REG_RES_READ16(bar_, reg_) \
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REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
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#define REG_RES_READ32(bar_, reg_) \
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REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
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#define REG_RES_WRITE8(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
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#define REG_RES_WRITE16(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
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#define REG_RES_WRITE32(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
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#define REG_RES_RMW8(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RMW16(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RXW8(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RXW16(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RXW32(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0)
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#define REG_RES_OR8(bar_, reg_, value_) \
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REG_RES_RMW8(bar_, reg_, 0xff, value_)
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#define REG_RES_OR16(bar_, reg_, value_) \
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REG_RES_RMW16(bar_, reg_, 0xffff, value_)
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#define REG_RES_OR32(bar_, reg_, value_) \
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REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
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#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
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#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
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#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
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#define REG_RES_XOR8(bar_, reg_, value_) \
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REG_RES_RXW8(bar_, reg_, 0xff, value_)
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#define REG_RES_XOR16(bar_, reg_, value_) \
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REG_RES_RXW16(bar_, reg_, 0xffff, value_)
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#define REG_RES_XOR32(bar_, reg_, value_) \
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REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
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#if CONFIG(SOC_INTEL_BAYTRAIL)
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/*
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* IO Sideband Function
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*/
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#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_IOSF, \
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REG_SCRIPT_SIZE_32, \
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reg_, mask_, value_, timeout_, unit_)
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#define REG_IOSF_READ(unit_, reg_) \
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REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
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#define REG_IOSF_WRITE(unit_, reg_, value_) \
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REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
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#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
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REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
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#define REG_IOSF_RXW(unit_, reg_, mask_, value_) \
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REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0)
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#define REG_IOSF_OR(unit_, reg_, value_) \
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REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
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#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
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#define REG_IOSF_XOR(unit_, reg_, value_) \
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REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_)
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#endif /* CONFIG_SOC_INTEL_BAYTRAIL */
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/*
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* CPU Model Specific Register
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*/
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#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_MSR, \
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REG_SCRIPT_SIZE_64, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_MSR_READ(reg_) \
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REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
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#define REG_MSR_WRITE(reg_, value_) \
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REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
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#define REG_MSR_RMW(reg_, mask_, value_) \
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REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
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#define REG_MSR_RXW(reg_, mask_, value_) \
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REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0)
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#define REG_MSR_OR(reg_, value_) \
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REG_MSR_RMW(reg_, -1ULL, value_)
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#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
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#define REG_MSR_XOR(reg_, value_) \
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REG_MSR_RXW(reg_, -1ULL, value_)
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/*
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* Chain to another table.
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*/
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#define REG_SCRIPT_NEXT(next_) \
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{ .command = REG_SCRIPT_COMMAND_NEXT, \
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.next = next_, \
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}
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/*
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* Set current device
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*/
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#define REG_SCRIPT_SET_DEV(dev_) \
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{ .command = REG_SCRIPT_COMMAND_SET_DEV, \
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.dev = dev_, \
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}
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/*
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* Last script entry. All tables need to end with REG_SCRIPT_END.
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*/
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#define REG_SCRIPT_END \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
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void reg_script_run(const struct reg_script *script);
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#ifdef __SIMPLE_DEVICE__
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void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step);
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#else
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void reg_script_run_on_dev(struct device *dev, const struct reg_script *step);
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#endif
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#endif /* REG_SCRIPT_H */
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