291 lines
10 KiB
C
291 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Serial Presence Detect (SPD) data stored on SDRAM modules.
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*
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* Datasheet:
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* - Name: PC SDRAM Serial Presence Detect (SPD) Specification
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* Revision 1.2A, December, 1997
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* - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
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*
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* Datasheet (alternative):
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* - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
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* JEDEC Standard No. 21-C
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* Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3):
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* - PDF: http://www.jedec.org/download/search/4_01_02_10R17.pdf
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*/
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#ifndef _SPD_H_
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#define _SPD_H_
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/* Byte numbers. */
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/* Number of bytes used by module manufacturer */
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#define SPD_NUM_MANUFACTURER_BYTES 0
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#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */
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#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */
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#define SPD_NUM_ROWS 3 /* Number of row address bits */
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/* Number of column address bits */
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#define SPD_NUM_COLUMNS 4
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/* Number of module rows (banks) */
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#define SPD_NUM_DIMM_BANKS 5
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#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */
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#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */
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/* Module interface signal levels */
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#define SPD_MODULE_VOLTAGE 8
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/* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
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#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
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/* SDRAM access time from clock (highest CAS latency), CAS access time (Tac,
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* tCAC)
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*/
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#define SPD_ACCESS_TIME_FROM_CLOCK 10
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#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */
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#define SPD_REFRESH 12 /* Refresh rate/type */
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#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */
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/* Error checking SDRAM (data) width */
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#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14
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/* SDRAM device attributes, minimum clock delay for back to back random
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* column
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*/
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#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15
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/* SDRAM device attributes, burst lengths supported */
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#define SPD_SUPPORTED_BURST_LENGTHS 16
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/* SDRAM device attributes, number of banks on SDRAM device */
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#define SPD_NUM_BANKS_PER_SDRAM 17
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/* SDRAM device attributes, CAS latency */
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#define SPD_ACCEPTABLE_CAS_LATENCIES 18
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/* SDRAM device attributes, CS latency */
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#define SPD_CS_LATENCY 19
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/* SDRAM device attributes, WE latency */
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#define SPD_WE_LATENCY 20
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#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */
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/* SDRAM device attributes, general */
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#define SPD_DEVICE_ATTRIBUTES_GENERAL 22
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/* SDRAM cycle time (2nd highest CAS latency) */
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#define SPD_SDRAM_CYCLE_TIME_2ND 23
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/* SDRAM access from clock (2nd highest CAS latency) */
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#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24
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/* SDRAM cycle time (3rd highest CAS latency) */
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#define SPD_SDRAM_CYCLE_TIME_3RD 25
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/* SDRAM access from clock (3rd highest CAS latency) */
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#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26
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/* Minimum row precharge time (Trp) */
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#define SPD_MIN_ROW_PRECHARGE_TIME 27
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/* Minimum row active to row active (Trrd) */
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#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28
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/* Minimum RAS to CAS delay (Trcd) */
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#define SPD_MIN_RAS_TO_CAS_DELAY 29
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/* Minimum RAS pulse width (Tras) */
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#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
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/* Density of each row on module */
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#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31
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/* Command and address signal input setup time */
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#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32
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/* Command and address signal input hold time */
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#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33
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/* Data signal input setup time */
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#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34
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#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
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#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */
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/* Internal write to read command delay (tWTR) */
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#define SPD_INT_WRITE_TO_READ_DELAY 37
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/* Internal read to precharge command delay (tRTP) */
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#define SPD_INT_READ_TO_PRECHARGE_DELAY 38
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/* Memory analysis probe characteristics */
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#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39
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/* Extension of byte 41 (tRC) and byte 42 (tRFC) */
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#define SPD_BYTE_41_42_EXTENSION 40
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/* Minimum active to active auto refresh (tRCmin) */
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#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41
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/* Minimum auto refresh to active/auto refresh (tRFC) */
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#define SPD_MIN_AUTO_REFRESH_TO_ACT 42
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/* Maximum device cycle time (tCKmax) */
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#define SPD_MAX_DEVICE_CYCLE_TIME 43
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/* Maximum skew between DQS and DQ (tDQSQ) */
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#define SPD_MAX_DQS_DQ_SKEW 44
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/* Maximum read data-hold skew factor (tQHS) */
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#define SPD_MAX_READ_DATAHOLD_SKEW 45
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#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */
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#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
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#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
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/* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
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#define SPD_MANUFACTURER_JEDEC_ID_CODE 64
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#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */
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/* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
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#define SPD_MANUFACTURER_PART_NUMBER 73
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#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */
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/* Manufacturing date (byte 93: year, byte 94: week) */
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#define SPD_MANUFACTURING_DATE 93
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/* Assembly serial number (bytes 95-98) */
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#define SPD_ASSEMBLY_SERIAL_NUMBER 95
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/* Manufacturer specific data (bytes 99-125) */
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#define SPD_MANUFACTURER_SPECIFIC_DATA 99
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/* Intel specification for frequency */
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#define SPD_INTEL_SPEC_FOR_FREQUENCY 126
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/* Intel specification details for 100MHz support */
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#define SPD_INTEL_SPEC_100_MHZ 127
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/* DRAM specifications use the following naming conventions for SPD locations */
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#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
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#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE
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#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY
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#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
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#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
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#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
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/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
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#define SPD_tRC 41
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/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
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#define SPD_tRFC 42
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/* SPD_MEMORY_TYPE values. */
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enum spd_memory_type {
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SPD_MEMORY_TYPE_UNDEFINED = 0x00,
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SPD_MEMORY_TYPE_FPM_DRAM = 0x01,
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SPD_MEMORY_TYPE_EDO = 0x02,
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SPD_MEMORY_TYPE_PIPELINED_NIBBLE = 0x03,
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SPD_MEMORY_TYPE_SDRAM = 0x04,
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SPD_MEMORY_TYPE_MULTIPLEXED_ROM = 0x05,
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SPD_MEMORY_TYPE_SGRAM_DDR = 0x06,
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SPD_MEMORY_TYPE_SDRAM_DDR = 0x07,
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SPD_MEMORY_TYPE_SDRAM_DDR2 = 0x08,
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SPD_MEMORY_TYPE_FBDIMM_DDR2 = 0x09,
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SPD_MEMORY_TYPE_FB_PROBE_DDR2 = 0x0a,
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SPD_MEMORY_TYPE_SDRAM_DDR3 = 0x0b,
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SPD_MEMORY_TYPE_DDR4_SDRAM = 0x0c,
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SPD_MEMORY_TYPE_DDR4E_SDRAM = 0x0e,
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SPD_MEMORY_TYPE_LPDDR3_SDRAM = 0x0f,
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SPD_MEMORY_TYPE_LPDDR4_SDRAM = 0x10,
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};
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/* SPD_MODULE_VOLTAGE values. */
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#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */
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#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */
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#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
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#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
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#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
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#define SPD_VOLTAGE_SSTL1 5 /* SSTL 1.8 */
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/* SPD_DIMM_CONFIG_TYPE values. */
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#define ERROR_SCHEME_NONE 0
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#define ERROR_SCHEME_PARITY 1
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#define ERROR_SCHEME_ECC 2
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/* SPD_ACCEPTABLE_CAS_LATENCIES values. */
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// TODO: Check values.
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#define SPD_CAS_LATENCY_1_0 0x01
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#define SPD_CAS_LATENCY_1_5 0x02
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#define SPD_CAS_LATENCY_2_0 0x04
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#define SPD_CAS_LATENCY_2_5 0x08
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#define SPD_CAS_LATENCY_3_0 0x10
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_4_0 0x40
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#define SPD_CAS_LATENCY_DDR2_2 (1 << 2)
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#define SPD_CAS_LATENCY_DDR2_3 (1 << 3)
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#define SPD_CAS_LATENCY_DDR2_4 (1 << 4)
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#define SPD_CAS_LATENCY_DDR2_5 (1 << 5)
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#define SPD_CAS_LATENCY_DDR2_6 (1 << 6)
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#define SPD_CAS_LATENCY_DDR2_7 (1 << 7)
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/* SPD_SUPPORTED_BURST_LENGTHS values. */
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_2 2
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#define SPD_BURST_LENGTH_4 4
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#define SPD_BURST_LENGTH_8 8
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#define SPD_BURST_LENGTH_PAGE (1 << 7)
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/* SPD_MODULE_ATTRIBUTES values. */
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#define MODULE_BUFFERED 1
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#define MODULE_REGISTERED 2
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/* DIMM SPD addresses */
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#define DIMM0 0x50
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#define DIMM1 0x51
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#define DIMM2 0x52
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#define DIMM3 0x53
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#define DIMM4 0x54
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#define DIMM5 0x55
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#define DIMM6 0x56
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#define DIMM7 0x57
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#define RC00 0
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#define RC01 1
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#define RC02 2
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#define RC03 3
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#define RC04 4
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#define RC05 5
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#define RC06 6
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#define RC07 7
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#define RC08 8
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#define RC09 9
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#define RC10 10
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#define RC11 11
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#define RC12 12
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#define RC13 13
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#define RC14 14
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#define RC15 15
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#define RC16 16
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#define RC17 17
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#define RC18 18
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#define RC19 19
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#define RC20 20
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#define RC21 21
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#define RC22 22
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#define RC23 23
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#define RC24 24
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#define RC25 25
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#define RC26 26
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#define RC27 27
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#define RC28 28
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#define RC29 29
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#define RC30 30
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#define RC31 31
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#define RC32 32
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#define RC33 33
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#define RC34 34
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#define RC35 35
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#define RC36 36
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#define RC37 37
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#define RC38 38
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#define RC39 39
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#define RC40 40
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#define RC41 41
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#define RC42 42
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#define RC43 43
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#define RC44 44
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#define RC45 45
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#define RC46 46
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#define RC47 47
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#define RC48 48
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#define RC49 49
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#define RC50 50
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#define RC51 51
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#define RC52 52
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#define RC53 53
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#define RC54 54
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#define RC55 55
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#define RC56 56
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#define RC57 57
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#define RC58 58
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#define RC59 59
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#define RC60 60
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#define RC61 61
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#define RC62 62
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#define RC63 63
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/* Byte 3: Module type information */
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#define SPD_UNDEFINED 0x00
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#define SPD_RDIMM 0x01
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#define SPD_UDIMM 0x02
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#define SPD_SODIMM 0x04
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#define SPD_72B_SO_CDIMM 0x06
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#define SPD_72B_SO_RDIMM 0x07
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#define SPD_MICRO_DIMM 0x08
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#define SPD_MINI_RDIMM 0x10
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#define SPD_MINI_UDIMM 0x20
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#define SPD_ECC_8BIT (1<<3)
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#endif
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