3ee54bbf94
Clone entirely from Cannonlake
commit id: 3487095304
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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#define MIPI_CLK (1 << 0)
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#define HDPLL_CLK (0 << 0)
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static void pch_enable_isclk(void)
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{
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pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
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pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
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}
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static void pch_handle_sideband(config_t *config)
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{
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if (config->pch_isclk)
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pch_enable_isclk();
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}
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static void pch_finalize(void)
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{
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struct device *dev;
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uint32_t reg32;
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uint16_t tcobase, tcocnt;
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uint8_t *pmcbase;
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config_t *config;
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uint8_t reg8;
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/* TCO Lock down */
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tcobase = smbus_tco_regs();
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tcocnt = inw(tcobase + TCO1_CNT);
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tcocnt |= TCO_LOCK;
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outw(tcocnt, tcobase + TCO1_CNT);
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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dev = PCH_DEV_PMC;
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config = dev->chip_info;
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pmcbase = pmc_mmio_regs();
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if (config->PmTimerDisabled) {
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reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
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reg8 |= (1 << 1);
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write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
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}
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/* Disable XTAL shutdown qualification for low power idle. */
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if (config->s0ix_enable) {
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reg32 = read32(pmcbase + CPPMVRIC);
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reg32 |= XTALSDQDIS;
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write32(pmcbase + CPPMVRIC, reg32);
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}
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pch_handle_sideband(config);
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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