985ff36bee
This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
177 lines
4.4 KiB
C
177 lines
4.4 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/exception.h>
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#include <libpayload.h>
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#include <stdint.h>
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void exception_test(void);
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static int test_abort;
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void exception_undefined_instruction(uint32_t *);
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void exception_software_interrupt(uint32_t *);
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void exception_prefetch_abort(uint32_t *);
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void exception_data_abort(uint32_t *);
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void exception_not_used(uint32_t *);
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void exception_irq(uint32_t *);
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void exception_fiq(uint32_t *);
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static void dump_stack(uintptr_t addr, size_t bytes)
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{
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int i, j;
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const int line = 8;
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uint32_t *ptr = (uint32_t *)(addr & ~(line * sizeof(*ptr) - 1));
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printf("Dumping stack:\n");
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for (i = bytes / sizeof(*ptr); i >= 0; i -= line) {
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printf("%p: ", ptr + i);
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for (j = i; j < i + line; j++)
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printf("%08x ", *(ptr + j));
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printf("\n");
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}
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}
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static void print_regs(uint32_t *regs)
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{
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int i;
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for (i = 0; i < 16; i++) {
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if (i == 15)
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printf("PC");
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else if (i == 14)
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printf("LR");
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else if (i == 13)
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printf("SP");
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else if (i == 12)
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printf("IP");
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else
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printf("R%d", i);
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printf(" = 0x%08x\n", regs[i]);
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}
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}
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void exception_undefined_instruction(uint32_t *regs)
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{
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printf("exception _undefined_instruction\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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void exception_software_interrupt(uint32_t *regs)
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{
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printf("exception _software_interrupt\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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void exception_prefetch_abort(uint32_t *regs)
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{
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printf("exception _prefetch_abort\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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void exception_data_abort(uint32_t *regs)
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{
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if (test_abort) {
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regs[15] = regs[0];
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return;
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} else {
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printf("exception _data_abort\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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}
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halt();
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}
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void exception_not_used(uint32_t *regs)
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{
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printf("exception _not_used\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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void exception_irq(uint32_t *regs)
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{
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printf("exception _irq\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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void exception_fiq(uint32_t *regs)
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{
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printf("exception _fiq\n");
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print_regs(regs);
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dump_stack(regs[13], 512);
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halt();
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}
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static inline uint32_t get_sctlr(void)
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{
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uint32_t val;
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asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
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return val;
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}
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static inline void set_sctlr(uint32_t val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0" :: "r" (val));
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asm volatile("" ::: "memory");
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}
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void exception_init(void)
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{
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static const uint32_t sctlr_te = (0x1 << 30);
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static const uint32_t sctlr_v = (0x1 << 13);
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static const uint32_t sctlr_a = (0x1 << 1);
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uint32_t sctlr = get_sctlr();
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/* Handle exceptions in ARM mode. */
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sctlr &= ~sctlr_te;
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/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
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sctlr &= ~sctlr_v;
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/* Enforce alignment temporarily. */
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set_sctlr(sctlr | sctlr_a);
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extern uint32_t exception_table[];
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set_vbar((uintptr_t)exception_table);
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test_abort = 1;
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exception_test();
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test_abort = 0;
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/* Restore alignment settings. */
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set_sctlr(sctlr);
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}
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