985ff36bee
This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
116 lines
2.8 KiB
ArmAsm
116 lines
2.8 KiB
ArmAsm
/*
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* This file is part of the libpayload project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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exception_stack:
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.align 5
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.skip 0x2000, 0xa5
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exception_stack_end:
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.word exception_stack_end
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exception_handler:
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.word 0
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.align 6
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.arm
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.global exception_table
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exception_table:
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b 1f
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b 2f
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b 3f
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b 4f
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b 5f
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b 6f
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b 7f
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b 8f
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1:
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ldr sp, _not_used
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b exception_common
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2:
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ldr sp, _undefined_instruction
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b exception_common
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3:
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ldr sp, _software_interrupt
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b exception_common
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4:
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ldr sp, _prefetch_abort
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b exception_common
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5:
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ldr sp, _data_abort
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b exception_common
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6:
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ldr sp, _not_used
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b exception_common
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7:
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ldr sp, _irq
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b exception_common
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8:
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ldr sp, _fiq
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b exception_common
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exception_common:
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str sp, exception_handler
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ldr sp, exception_stack_end
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push { lr }
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stmfd sp, { sp, lr }^
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sub sp, sp, $8
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push { r0 - r12 }
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mov r0, sp
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mov lr, pc
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ldr pc, exception_handler
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pop { r0 - r12 }
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add sp, sp, $8
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ldmfd sp!, { pc }^
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_undefined_instruction: .word exception_undefined_instruction
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_software_interrupt: .word exception_software_interrupt
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_prefetch_abort: .word exception_prefetch_abort
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_data_abort: .word exception_data_abort
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_not_used: .word exception_not_used
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_irq: .word exception_irq
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_fiq: .word exception_fiq
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.thumb
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.global set_vbar
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.thumb_func
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set_vbar:
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mcr p15, 0, r0, c12, c0, 0
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bx lr
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.global exception_test
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.thumb_func
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exception_test:
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mov r1, $1
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mov r0, pc
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add r0, $3
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ldr r1, [r1]
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bx lr
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