Lijian Zhao 0e9bbcc905 intel/fsp: Update Cannonlake FSP header ... Update Cannonlake FSP header to version 7.x.2E.50, the following changes were made, Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 2. Remove Fixed mid option for SaGv. 3. Add DualDimm per channel board type. 4. Remove PEG IMR options. Silicon Init UPD: 1. Add CD clock selections of 675MHz. 2. Remove Pcode PreWake/Rampup/RampDn time selections. 3. Remove C3 state demotion/unDemotion selections. BUG=None TEST=Build and boot up on meowth platform. Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26148 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-05-18 12:19:56 +00:00
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edk2	vendorcode/intel: Add UDK2017 support	2018-01-31 05:56:07 +00:00
fsp	intel/fsp: Update Cannonlake FSP header	2018-05-18 12:19:56 +00:00
fsp1_0	vendorcode/intel/fsp1_0: Don't break GCC strict aliasing	2016-05-13 17:34:13 +02:00
Kconfig	vendorcode/intel: Add Kconfig option to get UDK_VERSION	2018-01-31 05:56:27 +00:00
Makefile.inc	vendorcode/intel: Add UDK2017 support	2018-01-31 05:56:07 +00:00