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Subrata Banik e88bee7219 soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:

Before:

Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

With this code change:

[SPEW ]  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ]  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ]  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ]  The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ]  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ]  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ]  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-03 04:57:58 +00:00
3rdparty Update vboot submodule to upstream main 2022-06-17 20:57:35 +00:00
Documentation Documentation/acronyms.md: Fix unmatched markdown symbols 2022-06-27 13:42:37 +00:00
LICENSES
configs nb/intel/gm45: Enable 64bit support 2022-05-13 10:57:41 +00:00
payloads payloads/tianocore: Show build options 2022-06-23 12:17:12 +00:00
spd spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCP 2022-06-17 14:32:56 +00:00
src soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S 2022-07-03 04:57:58 +00:00
tests lib: Check for non-existent DIMMs in check_if_dimm_changed 2022-04-20 06:57:21 +00:00
util util/amdfwtool: Initalize all variables before use 2022-06-30 19:08:14 +00:00
.checkpatch.conf checkpatch.conf: Disable gerrit change ID for coreboot 2022-04-12 20:39:50 +00:00
.clang-format
.editorconfig
.gitignore Treewide: Remove doxygen config files and targets 2022-05-28 01:24:51 +00:00
.gitmodules tests: update CMocka to stable-1.1 2022-04-19 13:00:36 +00:00
.gitreview
.mailmap .mailmap: Add a .mailmap file for git 2022-03-08 18:53:47 +00:00
AUTHORS
COPYING
MAINTAINERS MAINTAINERS: Add Maintainers for Intel Elkhart Lake SoC 2022-06-05 21:07:26 +00:00
Makefile Makefile: Update error if building real-all when NOCOMPILE is set 2022-06-28 02:34:44 +00:00
Makefile.inc cbfstool: Expand CBFS verification validity check 2022-06-07 12:57:25 +00:00
README.md Treewide: Remove doxygen config files and targets 2022-05-28 01:24:51 +00:00
gnat.adc
toolchain.inc build system: immediately report what users are supposed to look into 2021-10-18 16:39:25 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.