e99e2b65cf
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <soc/ramstage.h>
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static void chip_init(void *chip_info)
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{
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/* Perform silicon specific init. */
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if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
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intel_silicon_init();
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else
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fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
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}
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static void chip_enable_dev(device_t dev)
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{
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const char *type_name = dev_path_name(dev->path.type);
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/* Set the operations if it is a special bus type */
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printk(BIOS_DEBUG, "type: %s\n", type_name);
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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}
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struct chip_operations soc_intel_quark_ops = {
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CHIP_NAME("Intel Quark")
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.init = &chip_init,
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.enable_dev = chip_enable_dev,
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};
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void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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struct soc_intel_quark_config *config;
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device_t dev;
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/* Locate the configuration data from devicetree.cb */
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dev = dev_find_slot(0, LPC_DEV_FUNC);
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if (!dev) {
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printk(BIOS_ERR,
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"Error! Device (PCI:0:%02x.%01x) not found, "
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"soc_silicon_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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return;
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}
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config = dev->chip_info;
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/* Set the parameters for SiliconInit */
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// printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
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SILICON_INIT_UPD *new)
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{
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/* Display the parameters for SiliconInit */
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// printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
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}
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