e9a0130879
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
395 lines
10 KiB
C
395 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "pch.h"
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typedef struct southbridge_intel_lynxpoint_config config_t;
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static u8 *usb_xhci_mem_base(device_t dev)
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{
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u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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/* Check if the controller is disabled or not present */
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if (mem_base == 0 || mem_base == 0xffffffff)
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return 0;
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return (u8 *)(mem_base & ~0xf);
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}
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static int usb_xhci_port_count_usb3(device_t dev)
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{
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if (pch_is_lp()) {
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/* LynxPoint-LP has 4 SS ports */
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return 4;
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}
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/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
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u8 *mem_base = usb_xhci_mem_base(dev);
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u32 fus = read32(mem_base + XHCI_USB3FUS);
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fus >>= XHCI_USB3FUS_SS_SHIFT;
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fus &= XHCI_USB3FUS_SS_MASK;
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switch (fus) {
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case 3: return 0;
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case 2: return 2;
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case 1: return 4;
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case 0:
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default: return 6;
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}
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}
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static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
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{
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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u32 status = read32(portsc);
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/* Do not set Port Enabled/Disabled field */
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status &= ~XHCI_USB3_PORTSC_PED;
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/* Clear all change status bits */
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status |= XHCI_USB3_PORTSC_CHST;
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write32(portsc, status);
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}
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static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
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{
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
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}
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#define XHCI_RESET_DELAY_US 1000 /* 1ms */
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#define XHCI_RESET_TIMEOUT 100 /* 100ms */
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/*
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* 1) Wait until port is done polling
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* 2) If port is disconnected
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* a) Issue warm port reset
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* b) Poll for warm reset complete
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* c) Write 1 to port change status bits
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*/
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static void usb_xhci_reset_usb3(device_t dev, int all)
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{
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u32 status, port_disabled;
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int timeout, port;
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int port_count = usb_xhci_port_count_usb3(dev);
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u8 *mem_base = usb_xhci_mem_base(dev);
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if (!mem_base || !port_count)
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return;
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/* Get mask of disabled ports */
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port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
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/* Wait until all enabled ports are done polling */
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for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
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int complete = 1;
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for (port = 0; port < port_count; port++) {
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/* Skip disabled ports */
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if (port_disabled & (1 << port))
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continue;
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/* Read port link status field */
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status = read32(mem_base + XHCI_USB3_PORTSC(port));
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status &= XHCI_USB3_PORTSC_PLS;
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if (status == XHCI_PLSR_POLLING)
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complete = 0;
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}
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/* Exit if all ports not polling */
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if (complete)
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break;
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udelay(XHCI_RESET_DELAY_US);
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}
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/* Reset all requested ports */
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for (port = 0; port < port_count; port++) {
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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/* Skip disabled ports */
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if (port_disabled & (1 << port))
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continue;
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status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
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/* Reset all or only disconnected ports */
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if (all || (status == XHCI_PLSR_RXDETECT ||
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status == XHCI_PLSR_POLLING))
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usb_xhci_reset_port_usb3(mem_base, port);
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else
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port_disabled |= 1 << port;
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}
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/* Wait for warm reset complete on all reset ports */
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for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
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int complete = 1;
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for (port = 0; port < port_count; port++) {
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/* Only check ports that were reset */
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if (port_disabled & (1 << port))
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continue;
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/* Check if warm reset is complete */
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status = read32(mem_base + XHCI_USB3_PORTSC(port));
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if (!(status & XHCI_USB3_PORTSC_WRC))
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complete = 0;
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}
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/* Check for warm reset complete in any port */
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if (complete)
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break;
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udelay(XHCI_RESET_DELAY_US);
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}
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/* Clear port change status bits */
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for (port = 0; port < port_count; port++)
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usb_xhci_reset_status_usb3(mem_base, port);
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}
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#ifdef __SMM__
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/* Handler for XHCI controller on entry to S3/S4/S5 */
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void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
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{
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u16 reg16;
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u32 reg32;
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u8 *mem_base = usb_xhci_mem_base(dev);
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if (!mem_base || slp_typ < ACPI_S3)
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return;
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if (pch_is_lp()) {
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/* Set D0 state */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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/* Clear PCI 0xB0[14:13] */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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pci_write_config32(dev, 0xb0, reg32);
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/* Clear MMIO 0x816c[14,2] */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~((1 << 14) | (1 << 2));
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write32(mem_base + 0x816c, reg32);
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/* Reset disconnected USB3 ports */
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usb_xhci_reset_usb3(dev, 0);
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/* Set MMIO 0x80e0[15] */
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reg32 = read32(mem_base + 0x80e0);
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reg32 |= (1 << 15);
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write32(mem_base + 0x80e0, reg32);
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}
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/* Set D3Hot state and enable PME */
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME);
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}
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/* Route all ports to XHCI controller */
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void usb_xhci_route_all(void)
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{
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u32 port_mask, route;
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u16 reg16;
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/* Skip if EHCI is already disabled */
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if (RCBA32(FD) & PCH_DISABLE_EHCI1)
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return;
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/* Set D0 state */
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reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16);
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/* Set USB3 superspeed enable */
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port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM);
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route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR);
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route &= ~XHCI_USB3PR_SSEN;
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route |= XHCI_USB3PR_SSEN & port_mask;
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pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route);
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/* Route USB2 ports to XHCI controller */
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port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM);
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route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR);
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route &= ~XHCI_USB2PR_HCSEL;
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route |= XHCI_USB2PR_HCSEL & port_mask;
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pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route);
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/* Disable EHCI controller */
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usb_ehci_disable(PCH_EHCI1_DEV);
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/* LynxPoint-H has a second EHCI controller */
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if (!pch_is_lp())
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usb_ehci_disable(PCH_EHCI2_DEV);
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/* Reset and clear port change status */
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usb_xhci_reset_usb3(PCH_XHCI_DEV, 1);
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}
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#else /* !__SMM__ */
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static void usb_xhci_clock_gating(device_t dev)
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{
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u32 reg32;
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u16 reg16;
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/* IOBP 0xE5004001[7:6] = 11b */
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pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
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reg32 = pci_read_config32(dev, 0x40);
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reg32 &= ~(1 << 23); /* unsupported request */
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if (pch_is_lp()) {
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/* D20:F0:40h[18,17,8] = 111b */
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reg32 |= (1 << 18) | (1 << 17) | (1 << 8);
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/* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */
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reg32 &= ~(1 << 19);
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reg32 |= (1 << 21) | (1 << 20);
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} else {
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/* D20:F0:40h[21,20,18,17,8] = 11111b */
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reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8);
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}
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/* Avoid writing upper byte as it is write-once */
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pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff));
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pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff));
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/* D20:F0:44h[9,7,3] = 111b */
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reg16 = pci_read_config16(dev, 0x44);
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reg16 |= (1 << 9) | (1 << 7) | (1 << 3);
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pci_write_config16(dev, 0x44, reg16);
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reg32 = pci_read_config32(dev, 0xa0);
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if (pch_is_lp()) {
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/* D20:F0:A0h[18] = 1 */
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reg32 |= (1 << 18);
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} else {
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/* D20:F0:A0h[6] = 1 */
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reg32 |= (1 << 6);
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}
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pci_write_config32(dev, 0xa0, reg32);
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/* D20:F0:A4h[13] = 0 */
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reg32 = pci_read_config32(dev, 0xa4);
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reg32 &= ~(1 << 13);
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pci_write_config32(dev, 0xa4, reg32);
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}
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static void usb_xhci_init(device_t dev)
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{
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u32 reg32;
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u16 reg16;
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u8 *mem_base = usb_xhci_mem_base(dev);
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config_t *config = dev->chip_info;
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/* D20:F0:74h[1:0] = 00b (set D0 state) */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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/* Enable clock gating first */
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usb_xhci_clock_gating(dev);
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reg32 = read32(mem_base + 0x8144);
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if (pch_is_lp()) {
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/* XHCIBAR + 8144h[8,7,6] = 111b */
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reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
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} else {
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/* XHCIBAR + 8144h[8,7,6] = 100b */
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reg32 &= ~((1 << 7) | (1 << 6));
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reg32 |= (1 << 8);
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}
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write32(mem_base + 0x8144, reg32);
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if (pch_is_lp()) {
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/* XHCIBAR + 816Ch[19:0] = 000e0038h */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~0x000fffff;
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reg32 |= 0x000e0038;
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write32(mem_base + 0x816c, reg32);
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/* D20:F0:B0h[17,14,13] = 100b */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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reg32 |= (1 << 17);
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pci_write_config32(dev, 0xb0, reg32);
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}
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reg32 = pci_read_config32(dev, 0x50);
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if (pch_is_lp()) {
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/* D20:F0:50h[28:0] = 0FCE2E5Fh */
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reg32 &= ~0x1fffffff;
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reg32 |= 0x0fce2e5f;
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} else {
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/* D20:F0:50h[26:0] = 07886E9Fh */
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reg32 &= ~0x07ffffff;
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reg32 |= 0x07886e9f;
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}
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pci_write_config32(dev, 0x50, reg32);
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/* D20:F0:44h[31] = 1 (Access Control Bit) */
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reg32 = pci_read_config32(dev, 0x44);
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reg32 |= (1UL << 31);
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pci_write_config32(dev, 0x44, reg32);
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/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
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reg32 = pci_read_config32(dev, 0x40);
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reg32 &= ~(1 << 23); /* unsupported request */
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reg32 |= (1UL << 31);
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pci_write_config32(dev, 0x40, reg32);
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if (acpi_is_wakeup_s3()) {
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/* Reset ports that are disabled or
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* polling before returning to the OS. */
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usb_xhci_reset_usb3(dev, 0);
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} else if (config->xhci_default) {
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/* Route all ports to XHCI */
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outb(0xca, 0xb2);
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}
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}
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static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
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unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = &usb_xhci_set_subsystem,
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};
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static struct device_operations usb_xhci_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = usb_xhci_init,
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.ops_pci = &lops_pci,
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};
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static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */
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0x9c31, /* LynxPoint-LP */
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0 };
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static const struct pci_driver pch_usb_xhci __pci_driver = {
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.ops = &usb_xhci_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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#endif /* !__SMM__ */
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