1eaf64c723
This change drops the inclusion of entry16.ld and reset16.ld and instead adds the content of those files directly in memlayout_x86.ld in amd/picasso. This is done to allow the work for top-aligning bootblock to happen independent of Picasso layout. Once that is complete, Picasso layout can be re-evaluated to see if it can make use of the common bootblock linker file includes. TEST=Verified that coreboot.rom generated using --timeless is the same with and without this change for trembyle. Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
116 lines
5.2 KiB
Text
116 lines
5.2 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <memlayout.h>
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#include <arch/header.ld>
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#include <soc/psp_transfer.h>
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#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr)
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#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr)
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#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr)
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#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr)
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/*
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*
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* +--------------------------------+
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* reserved_dram_end +--------------------------------+
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* | |
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* | verstage (if reqd) |
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* | (VERSTAGE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR
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* | |
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* | FSP-M |
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* | (FSP_M_SIZE) |
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* +--------------------------------+ FSP_M_ADDR
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* | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
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* | romstage |
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* | (ROMSTAGE_SIZE) |
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* +--------------------------------+ ROMSTAGE_ADDR
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* | bootblock |
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* | (C_ENV_BOOTBLOCK_SIZE) |
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* +--------------------------------+ BOOTBLOCK_ADDR
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* | Unused hole |
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* +--------------------------------+
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* | FMAP cache (FMAP_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
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* | Early Timestamp region (512B) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
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* | Preram CBMEM console |
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* | (PRERAM_CBMEM_CONSOLE_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
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* | PSP shared (vboot workbuf) |
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* |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40
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* | Transfer Info Structure |
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* +--------------------------------+ PSP_SHAREDMEM_BASE
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* | APOB (64KiB) |
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* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
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* | Early BSP stack |
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* | (EARLYRAM_BSP_STACK_SIZE) |
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* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
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* | DRAM |
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* +--------------------------------+ 0x100000
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* | Option ROM |
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* +--------------------------------+ 0xc0000
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* | Legacy VGA |
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* +--------------------------------+ 0xa0000
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* | DRAM |
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* +--------------------------------+ 0x0
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*/
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SECTIONS
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{
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DRAM_START(0x0)
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EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE)
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EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE)
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REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1)
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#if CONFIG(VBOOT)
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PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
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#endif
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#include "memlayout_transfer_buffer.inc"
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#if CONFIG(VBOOT)
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PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
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#endif
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_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
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_ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
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BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
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ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
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REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)
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#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
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VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
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#endif
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EARLY_RESERVED_DRAM_END(.)
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RAMSTAGE(CONFIG_RAMBASE, 8M)
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}
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#if ENV_BOOTBLOCK
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gdtptr16_offset = gdtptr16 & 0xffff;
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nullidt_offset = nullidt & 0xffff;
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SECTIONS {
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/* Trigger an error if I have an unusable start address */
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_TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
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_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
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. = CONFIG_X86_RESET_VECTOR;
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.reset . : {
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*(.reset);
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. = 15;
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BYTE(0x00);
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}
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}
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#endif /* ENV_BOOTBLOCK */
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