6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <types.h>
|
|
#include <console/console.h>
|
|
#include <acpi/acpi.h>
|
|
#include <device/device.h>
|
|
#include <device/pci_ops.h>
|
|
#include "haswell.h"
|
|
#include <southbridge/intel/lynxpoint/pch.h>
|
|
|
|
unsigned long acpi_fill_mcfg(unsigned long current)
|
|
{
|
|
struct device *dev;
|
|
u32 pciexbar = 0;
|
|
u32 pciexbar_reg;
|
|
int max_buses;
|
|
u32 mask;
|
|
|
|
dev = pcidev_on_root(0, 0);
|
|
if (!dev)
|
|
return current;
|
|
|
|
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
|
|
|
|
/* MMCFG not supported or not enabled. */
|
|
if (!(pciexbar_reg & (1 << 0)))
|
|
return current;
|
|
|
|
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
|
|
switch ((pciexbar_reg >> 1) & 3) {
|
|
case 0: /* 256MB */
|
|
pciexbar = pciexbar_reg & mask;
|
|
max_buses = 256;
|
|
break;
|
|
case 1: /* 128M */
|
|
mask |= (1 << 27);
|
|
pciexbar = pciexbar_reg & mask;
|
|
max_buses = 128;
|
|
break;
|
|
case 2: /* 64M */
|
|
mask |= (1 << 27) | (1 << 26);
|
|
pciexbar = pciexbar_reg & mask;
|
|
max_buses = 64;
|
|
break;
|
|
default: /* RSVD */
|
|
return current;
|
|
}
|
|
|
|
if (!pciexbar)
|
|
return current;
|
|
|
|
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
|
|
max_buses - 1);
|
|
|
|
return current;
|
|
}
|
|
|
|
static unsigned long acpi_fill_dmar(unsigned long current)
|
|
{
|
|
struct device *const igfx_dev = pcidev_on_root(2, 0);
|
|
const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
|
|
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
|
|
const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
|
|
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
|
|
|
|
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
|
|
if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
|
|
|
|
const unsigned long tmp = current;
|
|
|
|
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
|
|
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
|
|
|
|
acpi_dmar_drhd_fixup(tmp, current);
|
|
}
|
|
|
|
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
|
|
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
|
|
|
|
const unsigned long tmp = current;
|
|
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
|
|
current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
|
|
PCH_IOAPIC_PCI_SLOT, 0);
|
|
|
|
size_t i;
|
|
for (i = 0; i < 8; ++i)
|
|
current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
|
|
PCH_HPET_PCI_SLOT, i);
|
|
acpi_dmar_drhd_fixup(tmp, current);
|
|
}
|
|
|
|
return current;
|
|
}
|
|
|
|
unsigned long northbridge_write_acpi_tables(const struct device *const dev,
|
|
unsigned long current,
|
|
struct acpi_rsdp *const rsdp)
|
|
{
|
|
/* Create DMAR table only if we have VT-d capability. */
|
|
const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
|
|
if (capid0_a & VTD_DISABLE)
|
|
return current;
|
|
|
|
acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
|
|
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
|
|
acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
|
|
current += dmar->header.length;
|
|
current = acpi_align_current(current);
|
|
acpi_add_table(rsdp, dmar);
|
|
|
|
return current;
|
|
}
|