f0f8a5fda8
Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
19 lines
645 B
Text
19 lines
645 B
Text
CONFIG_VENDOR_MSI=y
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CONFIG_CBFS_SIZE=0x1000000
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_TIANOCORE_BOOT_TIMEOUT=3
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CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
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CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
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CONFIG_PCIEXP_HOTPLUG=y
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CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
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CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
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CONFIG_POST_DEVICE_PCI_PCIE=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_TIANOCORE=y
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CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
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CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
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CONFIG_TIANOCORE_CBMEM_LOGGING=y
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CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
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CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
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CONFIG_TPM2=y
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CONFIG_TPM_MEASURED_BOOT=y
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