coreboot-kgpe-d16/src/include/device/i2c.h
Duncan Laurie ec00968f08 device: i2c: Add support for I2C bus operations
In order to support doing bus operations on an I2C device that is
described in the devicetree there needs to be some linkage of the
device and the existing opaque I2C controller bus number.

This is provided in a similar fashion to the existing SMBUS operations
but modified to fit within the existing I2C infrastructure.

Variants of the existing I2C helper functions are provided that will
obtain the bus number that corresponds to this device by looking for
the SOC-provided I2C bus operation structure to provide a function
that will make that translation.

For example an SOC using a PCI I2C controller at 0:15.0 could use:

soc/intel/.../i2c.c:
  static int i2c_dev_to_bus(struct device *dev)
  {
    if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0))
      return 0;
    return -1;
  }
  static struct i2c_bus_operation i2c_bus_ops = {
    .dev_to_bus = &i2c_dev_to_bus
  }
  static struct device_operations i2c_dev_ops = {
    .ops_i2c_bus = &i2c_bus_ops
    ...
  }

With an I2C device on that bus at address 0x1a described in the tree:

devicetree.cb:
  device pci 15.0 on # I2C0
    chip drivers/i2c/sample
      device i2c 1a.0 on end
    end
  end

That driver can then do I2C transactions with the device object
without needing to know that the SOC-specific bus number that this
I2C device lives on is "0".

For example it could read a version value from register address 0
with a byte transaction:

drivers/i2c/sample/sample.c:
  static void i2c_sample_enable(struct device *dev)
  {
    uint8_t ver;
    if (!i2c_dev_readb(dev, 0x00, &ver))
      printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver);
  }

Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15100
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:05:40 +02:00

193 lines
5.2 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DEVICE_I2C_H_
#define _DEVICE_I2C_H_
#include <stdint.h>
#include <stdlib.h>
enum i2c_speed {
I2C_SPEED_STANDARD = 100000,
I2C_SPEED_FAST = 400000,
I2C_SPEED_FAST_PLUS = 1000000,
I2C_SPEED_HIGH = 3400000,
I2C_SPEED_FAST_ULTRA = 5000000,
};
enum i2c_address_mode {
I2C_MODE_7_BIT,
I2C_MODE_10_BIT
};
struct i2c_seg
{
int read;
uint8_t chip;
uint8_t *buf;
int len;
};
int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count);
#define SOFTWARE_I2C_MAX_BUS 10 /* increase as necessary */
struct software_i2c_ops {
void (*set_sda)(unsigned bus, int high);
void (*set_scl)(unsigned bus, int high);
int (*get_sda)(unsigned bus);
int (*get_scl)(unsigned bus);
};
extern struct software_i2c_ops *software_i2c[];
int software_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count);
void software_i2c_wedge_ack(unsigned bus, u8 chip);
void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bit_count);
void software_i2c_wedge_write(unsigned bus, u8 chip, u8 reg, int bit_count);
int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data,
uint8_t mask, uint8_t shift);
int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data,
uint8_t mask, uint8_t shift);
/*
* software_i2c is supposed to be a debug feature. It's usually not compiled in,
* but when it is it can be dynamically enabled at runtime for certain busses.
* Need this ugly stub to arbitrate since I2C device drivers hardcode
* 'i2c_transfer()' as their entry point.
*/
static inline int i2c_transfer(unsigned bus, struct i2c_seg *segments,
int count)
{
if (CONFIG_SOFTWARE_I2C)
if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus])
return software_i2c_transfer(bus, segments, count);
return platform_i2c_transfer(bus, segments, count);
}
/*
* Read a raw chunk of data in one segment and one frame.
*
* [start][slave addr][r][data][stop]
*/
static inline int i2c_read_raw(unsigned bus, uint8_t chip, uint8_t *data,
int len)
{
struct i2c_seg seg =
{ .read = 1, .chip = chip, .buf = data, .len = len };
return i2c_transfer(bus, &seg, 1);
}
/*
* Write a raw chunk of data in one segment and one frame.
*
* [start][slave addr][w][data][stop]
*/
static inline int i2c_write_raw(unsigned bus, uint8_t chip, uint8_t *data,
int len)
{
struct i2c_seg seg =
{ .read = 0, .chip = chip, .buf = data, .len = len };
return i2c_transfer(bus, &seg, 1);
}
/**
* Read multi-bytes with two segments in one frame
*
* [start][slave addr][w][register addr][start][slave addr][r][data...][stop]
*/
static inline int i2c_read_bytes(unsigned bus, uint8_t chip, uint8_t reg,
uint8_t *data, int len)
{
struct i2c_seg seg[2];
seg[0].read = 0;
seg[0].chip = chip;
seg[0].buf = &reg;
seg[0].len = 1;
seg[1].read = 1;
seg[1].chip = chip;
seg[1].buf = data;
seg[1].len = len;
return i2c_transfer(bus, seg, ARRAY_SIZE(seg));
}
/**
* Read a byte with two segments in one frame
*
* [start][slave addr][w][register addr][start][slave addr][r][data][stop]
*/
static inline int i2c_readb(unsigned bus, uint8_t chip, uint8_t reg,
uint8_t *data)
{
struct i2c_seg seg[2];
seg[0].read = 0;
seg[0].chip = chip;
seg[0].buf = &reg;
seg[0].len = 1;
seg[1].read = 1;
seg[1].chip = chip;
seg[1].buf = data;
seg[1].len = 1;
return i2c_transfer(bus, seg, ARRAY_SIZE(seg));
}
/**
* Write a byte with one segment in one frame.
*
* [start][slave addr][w][register addr][data][stop]
*/
static inline int i2c_writeb(unsigned bus, uint8_t chip, uint8_t reg,
uint8_t data)
{
struct i2c_seg seg;
uint8_t buf[] = {reg, data};
seg.read = 0;
seg.chip = chip;
seg.buf = buf;
seg.len = ARRAY_SIZE(buf);
return i2c_transfer(bus, &seg, 1);
}
/* I2C bus operation for ramstage drivers */
struct device;
struct i2c_bus_operations {
/*
* This is an SOC specific method that can be provided to translate the
* 'struct device' for an I2C controller into a unique I2C bus number.
* Returns -1 if the bus number for this device cannot be determined.
*/
int (*dev_to_bus)(struct device *dev);
};
/* Return I2C bus number for provided device, -1 if not found */
int i2c_dev_find_bus(struct device *dev);
/* Variants of I2C helper functions that take a device instead of bus number */
int i2c_dev_transfer(struct device *dev, struct i2c_seg *segments, int count);
int i2c_dev_readb(struct device *dev, uint8_t reg, uint8_t *data);
int i2c_dev_writeb(struct device *dev, uint8_t reg, uint8_t data);
int i2c_dev_read_bytes(struct device *dev, uint8_t reg, uint8_t *data, int len);
int i2c_dev_read_raw(struct device *dev, uint8_t *data, int len);
int i2c_dev_write_raw(struct device *dev, uint8_t *data, int len);
#endif /* _DEVICE_I2C_H_ */