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Aladyshev Konstantin ec3daf7e08 Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table
H8QGI board has 2 IO-APICS with 56 IRQ’s:

IOAPIC[0]: GSI  0-23   - SB700 southbridge
IOAPIC[1]: GSI 24-55   - RD890 northbridge

`gDefaultApicDeviceInfoTable[]` structure in northbridge code

    vendorcode/amd/cimx/rd890/nbIoApic.c

has IO-APIC interrupt mapping for HT and IOMMU set to last 31
IRQ pin (24+31=55).

    CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
    // Group  Swizzling   Port Int Pin
      {0,     0,          31},   //HT
      {0,     0,          31},   //IOMMU
    […]

Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT.

Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2047
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-21 15:43:38 +01:00
3rdparty@7eb78b1109 Update 3rdparty to it's HEAD 2012-12-12 06:02:46 +01:00
documentation Add multi-architecture support to cbfstool 2012-11-30 00:42:31 +01:00
payloads PDcurses: Delete automatically created (and unused) files 2012-12-20 14:46:29 +01:00
src Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table 2012-12-21 15:43:38 +01:00
util cbfstool: Align the column of build hint message. 2012-12-14 08:46:26 +01:00
.gitignore Utility to dump boot timing table 2012-11-12 03:35:20 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING
Makefile Fix broken scan-build 2012-12-14 22:21:10 +01:00
Makefile.inc Rename devices -> device 2012-11-30 23:59:58 +01:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.