ec5e5e0db2
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
103 lines
2.3 KiB
Text
103 lines
2.3 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if BOARD_GOOGLE_NYAN_BLAZE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_ARM
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select BOARD_ID_SUPPORT
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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select EC_SOFTWARE_SYNC
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select SOC_NVIDIA_TEGRA124
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select TEGRA124_MODEL_CD570M
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select BOARD_ROMSIZE_KB_1024
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select SPI_FLASH
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select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
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select TERTIARY_BOARD_ID
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select VIRTUAL_DEV_SWITCH
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config MAINBOARD_DIR
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string
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default google/nyan_blaze
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config MAINBOARD_PART_NUMBER
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string
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default "Nyan Blaze"
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choice
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prompt "BCT boot media"
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default NYAN_BLAZE_BCT_CFG_SPI
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help
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Which boot media to configure the BCT for.
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config NYAN_BLAZE_BCT_CFG_SPI
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bool "SPI"
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help
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Configure the BCT for booting from SPI.
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config NYAN_BLAZE_BCT_CFG_EMMC
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bool "eMMC"
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help
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Configure the BCT for booting from eMMC.
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endchoice
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config BOOT_MEDIA_SPI_BUS
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int "SPI bus with boot media ROM"
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range 1 6
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depends on NYAN_BLAZE_BCT_CFG_SPI
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default 4
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help
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Which SPI bus the boot media is connected to.
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config BOOT_MEDIA_SPI_CHIP_SELECT
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int "Chip select for SPI boot media"
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range 0 3
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depends on NYAN_BLAZE_BCT_CFG_SPI
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default 0
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help
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Which chip select to use for boot media.
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 1
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3 if VBOOT2_VERIFY_FIRMWARE
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default 0x2
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config FLASHMAP_OFFSET
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hex
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default 0x00100000
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x2
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x20
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endif # BOARD_GOOGLE_NYAN_BLAZE
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