86391f1605
Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
14 lines
483 B
Makefile
14 lines
483 B
Makefile
## TSS
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verstage-$(CONFIG_TPM) += tss/tcg-1.2/tss.c
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verstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss_marshaling.c
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verstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss.c
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ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y)
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romstage-$(CONFIG_TPM) += tss/tcg-1.2/tss.c
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romstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss_marshaling.c
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romstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss.c
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endif # CONFIG_VBOOT_SEPARATE_VERSTAGE
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ramstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss_marshaling.c
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ramstage-$(CONFIG_TPM2) += tss/tcg-2.0/tss.c
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