33b535f15d
On those chipsets the pins are just a legacy concept. Real interrupts are messages on corresponding busses or some internal logic of chipset. Hence interrupt routing isn't anymore board-specific (dependent on layout) but depends only on configuration. Rather than attempting to sync real config, ACPI and legacy descriptors, just use the same interrupt routing per chipset covering all possible devices. The only part which remains board-specific are LPC and PCI interrupts. Interrupt balancing may suffer from such merge but: a) Doesn't seem to be the case of this map on current systems b) Almost all OS use MSI nowadays bypassing this stuff completely c) If we want a good balancing we need to take into account that e.g. wlan card may be placed in a different slot and so would require complicated balancing on runtime. It's difficult to maintain with almost no benefit. Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7130 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
102 lines
3.4 KiB
Text
102 lines
3.4 KiB
Text
chip northbridge/intel/sandybridge
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
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register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
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register "gpu_panel_power_down_delay" = "150" # T3: 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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# Coordinate with HW_ALL
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register "pstate_coord_type" = "0xfe"
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register "tcc_offset" = "5" # TCC of 95C
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register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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subsystemid 0x1ae0 0xc000 inherit
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "alt_gp_smi_en" = "0x0002"
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register "gpi1_routing" = "1"
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register "gpi6_routing" = "2"
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register "sata_port_map" = "0x3"
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# Set max SATA speed to 3.0 Gb/s
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register "sata_interface_speed_support" = "0x2"
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# Enable EC Port 0x68/0x6C
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register "gen1_dec" = "0x00040069"
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# EC range is 0x800-0x9ff
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register "gen2_dec" = "0x00fc0901"
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# EC range is 0x1610-0x161F
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register "gen3_dec" = "0x0001C1611"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth)
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2 (WLAN)
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device pci 1c.2 on end # PCIe Port #3 (Card Reader)
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register "pcie_aspm_f2" = "0x3"
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 (LAN)
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/quanta/it8518
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# 60h/64h KBC
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller 1 (HDD/SSD)
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device pci 1f.3 on end # SMBus Controller
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device pci 1f.5 off end # SATA Controller 2 (MSATA)
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device pci 1f.6 off end # Thermal
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end
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end
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end
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