ef8b95745f
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
43 lines
1.1 KiB
Text
43 lines
1.1 KiB
Text
config SOUTHBRIDGE_INTEL_COMMON
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_GPIO
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMBUS
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def_bool n
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select HAVE_DEBUG_SMBUS
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config SOUTHBRIDGE_INTEL_COMMON_SPI
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def_bool n
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select SPI_FLASH
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config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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config HAVE_INTEL_CHIPSET_LOCKDOWN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMM
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def_bool n
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config INTEL_DESCRIPTOR_MODE_CAPABLE
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def_bool n
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help
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This config simply states that the platform is *capable* of running in
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descriptor mode (when the descriptor in flash is valid).
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config INTEL_CHIPSET_LOCKDOWN
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depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
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#ChromeOS's payload seems to handle finalization on its on.
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bool "Lock down chipset in coreboot"
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default y
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help
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Some registers within host bridge on particular chipsets should be
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locked down on each normal boot path (done by either coreboot or payload)
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and S3 resume (always done by coreboot). Select this to let coreboot
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to do this on normal boot path.
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