ef9136ff25
The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. coreboot logs appear as below with this patch: On First boot after flashing the image: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... CPU: Genuine Intel(R) 0000 CPU: ID 906a0, Alderlake Platform, ucode: 0000001a .. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 32 FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Erasing flash addr 0 + 4 KiB Update of PMC Descriptor successful, trigger GLOBAL RESET Next boot after GLOBAL RESET: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... .. FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Update of PMC Descriptor is not required! VBOOT: Loading verstage. .. CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> |
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| configs | ||
| Documentation | ||
| LICENSES | ||
| payloads | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| gnat.adc | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| toolchain.inc | ||
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.