c4e90454f4
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
44 lines
1 KiB
Text
44 lines
1 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_extern.asl>
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#if CONFIG(CHROMEOS_NVS)
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/* ChromeOS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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/* Operating system enumeration. */
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Name (OSYS, 0)
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/* Zero => PIC mode, One => APIC Mode */
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Name (PICM, Zero)
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/* Power state (AC = 1) */
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Name (PWRS, One)
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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PICM = Arg0
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}
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#if CONFIG(ECAM_MMCONF_SUPPORT)
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Scope(\_SB) {
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/* Base address of PCIe config space */
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Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
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/* Length of PCIe config space, 1MB each bus */
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Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
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/* PCIe Configuration Space */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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}
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#endif
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