5ac82dcc20
AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
39 lines
877 B
C
39 lines
877 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/helpers.h>
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#include <commonlib/mem_pool.h>
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void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
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{
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void *p;
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if (mp->alignment == 0)
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return NULL;
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/* We assume that mp->buf started mp->alignment aligned */
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sz = ALIGN_UP(sz, mp->alignment);
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/* Determine if any space available. */
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if ((mp->size - mp->free_offset) < sz)
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return NULL;
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p = &mp->buf[mp->free_offset];
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mp->free_offset += sz;
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mp->second_to_last_alloc = mp->last_alloc;
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mp->last_alloc = p;
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return p;
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}
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void mem_pool_free(struct mem_pool *mp, void *p)
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{
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/* Determine if p was the most recent allocation. */
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if (p == NULL || mp->last_alloc != p)
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return;
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mp->free_offset = mp->last_alloc - mp->buf;
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mp->last_alloc = mp->second_to_last_alloc;
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/* No way to track allocation before this one. */
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mp->second_to_last_alloc = NULL;
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}
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