Sugnan Prabhu S f040f759d9 soc/intel/alderlake: Enable logging of wake sources for S0ix ... This change adds elog.c and xhci.c to smm-y for alderlake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:183684923 TEST=Verified on Brya that entry/exit for S0ix are logged in eventlogs. 295 | 2021-03-29 10:31:48 | S0ix Enter 296 | 2021-03-29 10:31:58 | S0ix Exit 297 | 2021-03-29 10:31:58 | Wake Source | RTC Alarm | 0 298 | 2021-03-29 10:32:30 | S0ix Enter 299 | 2021-03-29 10:32:55 | S0ix Exit 300 | 2021-03-29 10:32:55 | Wake Source | Power Button | 0 301 | 2021-03-29 10:32:55 | EC Event | Power Button 305 | 2021-03-29 10:43:13 | S0ix Enter 306 | 2021-03-29 10:43:14 | S0ix Exit 307 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 308 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 309 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8 310 | 2021-03-29 10:43:14 | Wake Source | GPE # | 109 Change-Id: Icc836caa797d3bc4e782c6a51492de23e7b49b71 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51839 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-03-30 15:37:18 +00:00
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alderlake	soc/intel/alderlake: Enable logging of wake sources for S0ix	2021-03-30 15:37:18 +00:00
apollolake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
baytrail	cbfs: Remove prog_locate() for stages and rmodules	2021-03-16 21:45:34 +00:00
braswell	soc/intel/braswell: Factor out common acpi_fill_madt	2021-03-12 15:41:35 +00:00
broadwell	{lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bit	2021-03-22 13:01:19 +00:00
cannonlake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
common	soc/intel/common/gpio: Add function to get GPIO index in group	2021-03-28 16:05:02 +00:00
denverton_ns	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
elkhartlake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
icelake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
jasperlake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
quark
skylake	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
tigerlake	soc/intel/tigerlake: Fix REG_BASE_SIZE	2021-03-28 16:04:44 +00:00
xeon_sp	soc/intel/xeon_sp: Prepare for CBnT BPM generation	2021-03-30 11:46:23 +00:00
Kconfig