coreboot-kgpe-d16/src
Paul Menzel f0813bb7ed AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h`
Unfortunately, an unneeded mainboard specific `pmio.h` was created
when merging the AMD Parmer and Thatcher ports.

Rudolf used the header from a more generic location

    southbridge/amd/agesa/hudson/hudson.h

doing the the ASUS F2A85-M port, but did not delete the `pmio.h`
now unused `pmio.h` header file.

So adapt AMD Parmer and Thatcher to use the Hudson one as done for
the ASUS F2A85-M and delete the now unused mainboard specific header
file `pmio.h` to avoid duplication.

Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-30 14:18:27 +01:00
..
arch armv7: change some unsigned ints to uint32_t 2013-03-30 03:33:40 +01:00
console dynamic cbmem: fix memconsole and timestamps 2013-03-23 19:44:25 +01:00
cpu exynos5250: Add function for configuring L2 cache 2013-03-29 22:24:31 +01:00
device ramstage: prepare for relocation 2013-03-21 18:01:38 +01:00
drivers x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
ec x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
include memrange: add 2 new range_entry routines 2013-03-29 20:11:28 +01:00
lib memrange: add 2 new range_entry routines 2013-03-29 20:11:28 +01:00
mainboard AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h` 2013-03-30 14:18:27 +01:00
northbridge sandybridge: add option to mark graphics memory write-combining. 2013-03-29 20:00:39 +01:00
southbridge AMD CIMx SB800: Update Kconfig help texts to new SATA mode default 2013-03-29 21:33:38 +01:00
superio x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
vendorcode chromeos: remove CACHE_ROM automatic selection 2013-03-29 20:10:57 +01:00
Kconfig dynamic cbmem: fix memconsole and timestamps 2013-03-23 19:44:25 +01:00