Martin Roth f09b4b6bee soc/amd/common: Refactor and consolidate code for spi base ... Previously, the spi base address code was using a number of different functions in a way that didn't work for use on the PSP. This patch consolidates all of that to a single saved value that gets the LPC SPI base address by default on X86, and allows the PSP to set it to a different value. BUG=b:159811539 TEST=Build with following patch to set the SPI speed in psp_verstage. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-26 21:04:25 +00:00
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common	soc/amd/common: Refactor and consolidate code for spi base	2020-07-26 21:04:25 +00:00
picasso	soc/amd/picasso: Update postcode value	2020-07-26 21:03:41 +00:00
stoneyridge	soc/amd/common: Refactor and consolidate code for spi base	2020-07-26 21:04:25 +00:00
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