f0aaa29989
This is common code for Intel SOC that can be shared. Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
97 lines
2.8 KiB
Makefile
97 lines
2.8 KiB
Makefile
subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../common
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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ramstage-y += memmap.c
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romstage-y += memmap.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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smm-y += tsc_freq.c
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ramstage-y += spi.c
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smm-y += spi.c
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ramstage-y += chip.c
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ramstage-y += gfx.c
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ramstage-y += iosf.c
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romstage-y += iosf.c
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ramstage-y += northcluster.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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romstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += cpu.c
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ramstage-y += pmutil.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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ramstage-y += smm.c
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ramstage-y += ehci.c
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ramstage-y += xhci.c
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ramstage-y += southcluster.c
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ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
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ramstage-y += sata.c
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ramstage-y += acpi.c
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ramstage-y += lpe.c
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ramstage-y += scc.c
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ramstage-y += emmc.c
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ramstage-y += lpss.c
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ramstage-y += pcie.c
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ramstage-y += sd.c
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ramstage-y += dptf.c
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ramstage-y += perf_power.c
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ramstage-y += stage_cache.c
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romstage-y += stage_cache.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += hda.c
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# Remove as ramstage gets fleshed out
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ramstage-y += placeholders.c
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CPPFLAGS_common += -Isrc/soc/intel/baytrail/
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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INTERMEDIATE:=baytrail_add_me
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
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$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
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$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
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else
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IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
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endif
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baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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printf "\n** WARNING **\n"
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printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
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printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
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printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
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printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
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$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
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endif
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(IFD_BIN_PATH) \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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ifeq ($(CONFIG_HAVE_ME_BIN),y)
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:$(CONFIG_ME_BIN_PATH) \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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# Add memory reference code blob.
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cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
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mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
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mrc.bin-position := $(CONFIG_MRC_BIN_ADDRESS)
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mrc.bin-type := 0xab
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PHONY += baytrail_add_me
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