Nikolai Vyssotski 177a402b6e soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ... EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-07 16:04:36 +00:00
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pci	soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB	2021-06-07 16:04:36 +00:00
fsp-acpi.c	soc/amd/common/fsp/fsp-acpi: add check for maximum table size	2021-05-05 18:35:29 +00:00
fsp_reset.c
Makefile.inc	soc/amd/common: Add Kconfig/Makefile support for common/fsp/*	2021-05-07 18:43:41 +00:00