coreboot-kgpe-d16/src/drivers/intel
Aaron Durbin f0ec82450b drivers/intel/fsp2_0: honor FSP revision for memory training data
Utilizing the FSP revision while saving the memory training data is
important because it means when the FSP is updated the memory training
is redone. The previous implementation was just using '0' as a revision.
Because of that behavior a retrain would not have been done on an FSP
upgrade.

BUG=chrome-os-partner:52679

Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15744
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19 20:18:34 +02:00
..
fsp1_0 Fix some cbmem.h includes 2016-06-17 00:18:28 +02:00
fsp1_1 drivers/intel/fsp1_1: align on using ACPI_Sx definitions 2016-07-15 08:31:09 +02:00
fsp2_0 drivers/intel/fsp2_0: honor FSP revision for memory training data 2016-07-19 20:18:34 +02:00
gma intel/gma: Fix VBT generation 2016-04-01 15:34:11 +02:00
i210 intel/i210: Change API for function mainboard_get_mac_address() 2016-07-05 06:27:44 +02:00
wifi drivers/intel/wifi: Add support for generating SSDT table 2016-06-02 05:36:08 +02:00