f1b58b7835
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
110 lines
3 KiB
C
110 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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* Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <ec/acpi/ec.h>
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#include <northbridge/intel/nehalem/nehalem.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include "dock.h"
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#include <drivers/intel/gma/int15.h>
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#include <cpu/x86/lapic.h>
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#include <device/pci.h>
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#include <drivers/lenovo/lenovo.h>
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#include <arch/acpigen.h>
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static acpi_cstate_t cst_entries[] = {
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{1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
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{2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
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{2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
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};
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int get_cst_entries(acpi_cstate_t **entries)
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{
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*entries = cst_entries;
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return ARRAY_SIZE(cst_entries);
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}
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static void mainboard_init(struct device *dev)
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{
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printk(BIOS_SPEW, "starting SPI configuration\n");
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/* Configure SPI. */
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RCBA32(0x3800) = 0x07ff0500;
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RCBA32(0x3804) = 0x3f046008;
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RCBA32(0x3808) = 0x0058efc0;
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RCBA32(0x384c) = 0x92000000;
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RCBA32(0x3850) = 0x00000a0b;
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RCBA32(0x3858) = 0x07ff0500;
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RCBA32(0x385c) = 0x04ff0003;
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RCBA32(0x3860) = 0x00020001;
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RCBA32(0x3864) = 0x00000fff;
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RCBA32(0x3874) = 0;
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RCBA32(0x3890) = 0xf8400000;
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RCBA32(0x3894) = 0x143b5006;
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RCBA32(0x3898) = 0x05200302;
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RCBA32(0x389c) = 0x0601209f;
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RCBA32(0x38b0) = 0x00000004;
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RCBA32(0x38b4) = 0x03040002;
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RCBA32(0x38c8) = 0x00002005;
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RCBA32(0x38c4) = 0x00802005;
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RCBA32(0x3804) = 0x3f04e008;
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printk(BIOS_SPEW, "SPI configured\n");
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}
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static void fill_ssdt(struct device *device)
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{
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drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
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}
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static void mainboard_enable(struct device *dev)
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{
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u16 pmbase;
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dev->ops->init = mainboard_init;
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dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
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pmbase = pci_read_config32(pcidev_on_root(0x1f, 0),
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PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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outl(0, pmbase + SMI_EN);
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enable_lapic();
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pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE,
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DEFAULT_GPIOBASE | 1);
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pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL,
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0x10);
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/* If we're resuming from suspend, blink suspend LED */
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if (acpi_is_wakeup_s3())
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ec_write(0x0c, 0xc7);
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
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GMA_INT15_PANEL_FIT_DEFAULT,
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GMA_INT15_BOOT_DISPLAY_LFP, 2);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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