f1b58b7835
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
328 lines
10 KiB
C
328 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static inline void write_emrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask);
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}
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static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_emrr_base.lo,
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relo_params->uncore_emrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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struct smm_relocation_params *relo_params)
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{
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u32 smbase;
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u32 iedbase;
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/* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num. */
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smbase = staggered_smbase;
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iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
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smbase, iedbase);
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/* All threads need to set IEDBASE and SMBASE to the relocated
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* handler region. However, the save state location depends on the
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* smm_save_state_in_msrs field in the relocation parameters. If
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* smm_save_state_in_msrs is non-zero then the CPUs are relocating
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* the SMM handler in parallel, and each CPUs save state area is
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* located in their respective MSR space. If smm_save_state_in_msrs
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* is zero then the SMM relocation is happening serially so the
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* save state is at the same default location for all CPUs. */
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if (relo_params->smm_save_state_in_msrs) {
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msr_t smbase_msr;
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msr_t iedbase_msr;
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smbase_msr.lo = smbase;
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smbase_msr.hi = 0;
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/* According the BWG the IEDBASE MSR is in bits 63:32. It's
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* not clear why it differs from the SMBASE MSR. */
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iedbase_msr.lo = 0;
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iedbase_msr.hi = iedbase;
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wrmsr(SMBASE_MSR, smbase_msr);
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wrmsr(IEDBASE_MSR, iedbase_msr);
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} else {
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em64t101_smm_state_save_area_t *save_state;
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
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sizeof(*save_state));
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save_state->smbase = smbase;
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save_state->iedbase = iedbase;
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}
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}
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/* Returns 1 if SMM MSR save state was set. */
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static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
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{
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msr_t smm_mca_cap;
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smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
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if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
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msr_t smm_feature_control;
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smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
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smm_feature_control.hi = 0;
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smm_feature_control.lo |= SMM_CPU_SAVE_EN;
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wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
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relo_params->smm_save_state_in_msrs = 1;
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}
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return relo_params->smm_save_state_in_msrs;
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}
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
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/* Determine if the processor supports saving state in MSRs. If so,
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* enable it before the non-BSPs run so that SMM relocation can occur
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* in parallel in the non-BSP CPUs. */
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if (cpu == 0) {
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/* If smm_save_state_in_msrs is 1 then that means this is the
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* 2nd time through the relocation handler for the BSP.
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* Parallel SMM handler relocation is taking place. However,
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* it is desired to access other CPUs save state in the real
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* SMM handler. Therefore, disable the SMM save state in MSRs
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* feature. */
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if (relo_params->smm_save_state_in_msrs) {
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msr_t smm_feature_control;
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smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
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smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
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wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
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} else if (bsp_setup_msr_save_state(relo_params))
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/* Just return from relocation handler if MSR save
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* state is enabled. In that case the BSP will come
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* back into the relocation handler to setup the new
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* SMBASE as well disabling SMM save state in MSRs. */
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return;
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}
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/* Make appropriate changes to the save state map. */
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update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED)
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write_smrr(relo_params);
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if (mtrr_cap.lo & EMRR_SUPPORTED) {
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write_emrr(relo_params);
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/* UNCORE_EMRR msrs are package level. Therefore, only
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* configure these MSRs on the BSP. */
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if (cpu == 0)
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write_uncore_emrr(relo_params);
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}
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}
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static u32 northbridge_get_base_reg(struct device *dev, int reg)
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{
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u32 value;
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value = pci_read_config32(dev, reg);
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/* Base registers are at 1MiB granularity. */
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value &= ~((1 << 20) - 1);
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return value;
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}
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static void fill_in_relocation_params(struct device *dev,
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struct smm_relocation_params *params)
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{
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u32 tseg_size;
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u32 tsegmb;
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u32 bgsm;
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u32 emrr_base;
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u32 emrr_size;
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int phys_bits;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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/* Some of the range registers are dependent on the number of physical
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* address bits supported. */
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phys_bits = cpuid_eax(0x80000008) & 0xff;
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/* The range bounded by the TSEGMB and BGSM registers encompasses the
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* SMRAM range as well as the IED range. However, the SMRAM available
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* to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
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*/
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tsegmb = northbridge_get_base_reg(dev, TSEG);
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bgsm = northbridge_get_base_reg(dev, BGSM);
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tseg_size = bgsm - tsegmb;
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params->smram_base = tsegmb;
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params->smram_size = 4 << 20;
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params->ied_base = tsegmb + params->smram_size;
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params->ied_size = tseg_size - params->smram_size;
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/* Adjust available SMM handler memory size. */
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
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emrr_base = (params->ied_base + (2 << 20)) & rmask;
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emrr_size = params->ied_size - (2 << 20);
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/* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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* on the number of physical address bits supported. */
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params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
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params->emrr_base.hi = 0;
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params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_emrr_base.lo = emrr_base;
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params->uncore_emrr_base.hi = 0;
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params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
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MTRR_PHYS_MASK_VALID;
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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{
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char *ied_base;
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struct ied_header ied = {
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.signature = "INTEL RSVD",
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.size = params->ied_size,
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.reserved = {0},
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};
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ied_base = (void *)params->ied_base;
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/* Place IED header at IEDBASE. */
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memcpy(ied_base, &ied, sizeof(ied));
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/* Zero out 32KiB at IEDBASE + 1MiB */
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memset(ied_base + (1 << 20), 0, (32 << 10));
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}
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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struct device *dev = SA_DEV_ROOT;
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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fill_in_relocation_params(dev, &smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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*perm_smbase = smm_reloc_params.smram_base;
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*perm_smsize = smm_reloc_params.smram_size;
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*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
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}
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void smm_initialize(void)
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{
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/* Clear the SMM state in the southbridge. */
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southbridge_smm_clear_state();
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/*
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* Run the relocation handler for on the BSP to check and set up
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* parallel SMM relocation.
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*/
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smm_initiate_relocation();
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if (smm_reloc_params.smm_save_state_in_msrs)
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printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
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}
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/* The default SMM entry can happen in parallel or serially. If the
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* default SMM entry is done in parallel the BSP has already setup
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* the saving state to each CPU's MSRs. At least one save state size
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* is required for the initial SMM entry for the BSP to determine if
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* parallel SMM relocation is even feasible. */
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void smm_relocate(void)
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{
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/*
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* If smm_save_state_in_msrs is non-zero then parallel SMM relocation
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* shall take place. Run the relocation handler a second time on the
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* BSP to do * the final move. For APs, a relocation handler always
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* needs to be run.
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*/
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if (smm_reloc_params.smm_save_state_in_msrs)
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smm_initiate_relocation_parallel();
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else if (!boot_cpu())
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smm_initiate_relocation();
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}
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void smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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