8ead1dc875
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
19 lines
537 B
Text
19 lines
537 B
Text
# layout for firmware residing at top of 4GB address space
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# +-------------+ <-- 4GB - ROM_SIZE / start of flash
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# | unspecified |
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# +-------------+ <-- 4GB - BIOS_SIZE
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# | FMAP |
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# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE
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# | CBFS |
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# +-------------+ <-- 4GB / end of flash
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FLASH@##ROM_BASE## ##ROM_SIZE## {
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BIOS@##BIOS_BASE## ##BIOS_SIZE## {
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##CONSOLE_ENTRY##
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##MRC_CACHE_ENTRY##
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##SMMSTORE_ENTRY##
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##SPD_CACHE_ENTRY##
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FMAP@##FMAP_BASE## ##FMAP_SIZE##
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COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
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}
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}
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