Furquan Shaikh 028200f75f x86/acpi_device: Add support for GPIO output polarity ... Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-10-07 18:05:30 +02:00
..
acpi	chromeos mainboards: remove chromeos.asl	2016-07-30 01:36:32 +02:00
spd	src/mainboard: Capitalize ROM, RAM, CPU and APIC	2016-08-14 19:06:25 +02:00
acpi_tables.c
board_info.txt
boardid.c
bootblock_mainboard.c	vboot: consolidate google_chromeec_early_init() calls	2016-08-25 22:50:17 +02:00
chromeos.c	chromeos mainboards: remove chromeos.asl	2016-07-30 01:36:32 +02:00
chromeos.fmd	chromeos.fmd: Mark RW_LEGACY as CBFS	2016-04-05 13:37:31 +02:00
cmos.layout	mainboard: Clean up boot_option/reboot_bits in cmos.layout	2016-08-17 00:27:42 +02:00
devicetree.cb	x86/acpi_device: Add support for GPIO output polarity	2016-10-07 18:05:30 +02:00
dsdt.asl	chromeos mainboards: remove chromeos.asl	2016-07-30 01:36:32 +02:00
ec.c
ec.h	mainboards,ec: provide common declaration for mainboard_ec_init()	2016-09-26 23:53:12 +02:00
fadt.c
gpio.h	skylake: gpio: Add support for setting 1.8V tolerant	2016-06-09 17:07:26 +02:00
Kconfig	Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS	2016-08-18 22:04:34 +02:00
Kconfig.name
mainboard.c	chromeos mainboards: remove chromeos.asl	2016-07-30 01:36:32 +02:00
Makefile.inc	skylake/mainboard: Define mainboard hook in bootblock	2016-07-28 05:17:03 +02:00
pei_data.c
ramstage.c
romstage.c
smihandler.c	mainboards/skylake: use common Chrome EC SMI helpers	2016-07-15 08:36:24 +02:00