32471729d9
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
114 lines
3 KiB
C
114 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include "chip.h"
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <soc/gfx.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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static const struct reg_script gpu_pre_vbios_script[] = {
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/* Make sure GFX is bus master with MMIO access */
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REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script gfx_post_vbios_script[] = {
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/* Set Lock bits */
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REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
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REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
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REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
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REG_SCRIPT_END
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};
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static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
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{
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reg_script_run_on_dev(dev, ops);
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}
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static void gfx_pre_vbios_init(device_t dev)
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{
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
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gfx_run_script(dev, gpu_pre_vbios_script);
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}
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static void gfx_post_vbios_init(device_t dev)
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{
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
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gfx_run_script(dev, gfx_post_vbios_script);
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}
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static void gfx_init(device_t dev)
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{
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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/* Pre VBIOS Init */
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gfx_pre_vbios_init(dev);
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/* Run VBIOS */
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pci_dev_init(dev);
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/* Post VBIOS Init */
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gfx_post_vbios_init(dev);
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}
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static void gfx_read_resources(device_t dev)
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{
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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pci_dev_read_resources(dev);
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#if IS_ENABLED(CONFIG_MARK_GRAPHICS_MEM_WRCOMB)
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struct resource *res;
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/* Set the graphics memory to write combining. */
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res = find_resource(dev, PCI_BASE_ADDRESS_2);
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if (res == NULL) {
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printk(BIOS_DEBUG, "GFX: memory resource not found.\n");
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return;
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}
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res->flags |= IORESOURCE_WRCOMB;
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#endif
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}
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static struct device_operations gfx_device_ops = {
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.read_resources = gfx_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = gfx_init,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver gfx_driver __pci_driver = {
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.ops = &gfx_device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = GFX_DEVID,
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};
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