coreboot-kgpe-d16/src/mainboard/samsung/lumpy/dsdt.asl
Matt DeVillier 13da730b9c samsung/lumpy: add board-specific USB port info
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.

Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.

Change-Id: Id98aa5f6dbdcbb8da4616d4fce6e7388f3ba4656
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-12 18:06:06 +00:00

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
// Some generic macros
#include "acpi/platform.asl"
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include "acpi/thermal.asl"
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
// mainboard specific devices
#include "acpi/mainboard.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}