coreboot-kgpe-d16/src
Raul E Rangel f56b784227 soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:25:19 +00:00
..
acpi cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
arch coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
commonlib coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
console lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00
cpu cpu/x86/64bit: Add code to call function in protected mode 2020-12-05 08:19:17 +00:00
device device: Drop unused HyperTransport code 2020-11-25 09:11:46 +00:00
drivers coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
ec src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
include coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
lib cbfs: Skip mcache in post-RAM stages before CBMEM is online 2020-12-08 21:38:57 +00:00
mainboard mb/google/volteer: Reorganize FMAP 2020-12-09 14:23:06 +00:00
northbridge nb/intel/ironlake: Introduce memmap.h 2020-12-07 15:58:55 +00:00
security cbfs: Add verification for RO CBFS metadata hash 2020-12-03 00:11:08 +00:00
soc soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104 2020-12-09 14:25:19 +00:00
southbridge sb/intel/common: Modify CONFIG_LOCK_MANAGEMENT_ENGINE behavior 2020-12-07 14:06:28 +00:00
superio src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
vendorcode vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB 2020-12-07 10:30:09 +00:00
Kconfig lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00