b0f81518b5
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
147 lines
4.5 KiB
C
147 lines
4.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <bootmode.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "ec.h"
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#include <ec/quanta/it8518/ec.h>
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#define GPIO_COUNT 7
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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/* Write Protect: GPIO7 */
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gpios->gpios[0].port = 7;
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gpios->gpios[0].polarity = ACTIVE_LOW;
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gpios->gpios[0].value = !get_write_protect_state();
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strncpy((char *)gpios->gpios[0].name,"write protect",
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GPIO_MAX_NAME_LENGTH);
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/* Recovery: Virtual switch */
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gpios->gpios[1].port = -1;
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gpios->gpios[1].polarity = ACTIVE_HIGH;
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gpios->gpios[1].value = get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
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/* Developer: Virtual switch */
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gpios->gpios[2].port = -1;
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gpios->gpios[2].polarity = ACTIVE_HIGH;
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gpios->gpios[2].value = get_developer_mode_switch();
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strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
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/* Lid Switch: Virtual switch */
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gpios->gpios[3].port = -1;
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gpios->gpios[3].polarity = ACTIVE_HIGH;
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gpios->gpios[3].value = get_lid_switch();
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strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
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/* Power Button: Virtual switch */
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gpios->gpios[4].port = -1;
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gpios->gpios[4].polarity = ACTIVE_HIGH;
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gpios->gpios[4].value = 0; /* Hard-code to de-asserted */
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strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
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/* Was VGA Option ROM loaded? */
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gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[5].polarity = ACTIVE_HIGH;
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gpios->gpios[5].value = gfx_get_init_done();
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strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
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/* EC is in RW mode when it isn't in recovery mode. */
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gpios->gpios[6].port = -1;
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gpios->gpios[6].polarity = ACTIVE_HIGH;
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gpios->gpios[6].value = !get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[6].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH);
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}
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#endif
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int get_write_protect_state(void)
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{
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return !get_gpio(7);
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}
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int get_lid_switch(void)
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{
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/* hard-code to open */
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return 1;
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}
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/* The dev-switch is virtual on Stout (and so handled elsewhere). */
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int get_developer_mode_switch(void)
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{
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return 0;
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}
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/*
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* The recovery-switch is virtual on Stout and is handled via the EC.
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* Stout recovery mode is only valid if RTC_PWR_STS is set and the EC
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* indicated the recovery keys were pressed. We use a global flag for
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* rec_mode to be used after RTC_POWER_STS has been cleared. This function
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* is complicated by romstage support, which can't use a global variable.
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* Note, rec_mode is the only time the EC is in RO mode, otherwise, RW.
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*/
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int get_recovery_mode_switch(void)
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{
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#ifdef __PRE_RAM__
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device_t dev = PCI_DEV(0, 0x1f, 0);
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#else
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static int ec_in_rec_mode = 0;
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static int ec_rec_flag_good = 0;
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u8 ec_status = ec_read(EC_STATUS_REG);
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u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
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printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n",
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__func__, ec_status, reg8 & RTC_BATTERY_DEAD);
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#ifdef __PRE_RAM__
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return (((reg8 & RTC_BATTERY_DEAD) != 0) &&
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((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
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#else
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if (!ec_rec_flag_good) {
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ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) &&
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((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
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ec_rec_flag_good = 1;
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}
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return ec_in_rec_mode;
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#endif
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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