a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <stdint.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <elog.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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static void log_power_and_resets(const struct chipset_power_state *ps)
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{
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if (ps->gen_pmcon1 & PWR_FLR) {
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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elog_add_event(ELOG_TYPE_PWROK_FAIL);
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}
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if (ps->gen_pmcon1 & SUS_PWR_FLR) {
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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}
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if (ps->gen_pmcon1 & RPS) {
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elog_add_event(ELOG_TYPE_RTC_RESET);
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}
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if (ps->tco_sts & SECOND_TO_STS) {
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elog_add_event(ELOG_TYPE_TCO_RESET);
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}
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if (ps->pm1_sts & PRBTNOR_STS) {
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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}
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if (ps->gen_pmcon1 & SRS) {
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elog_add_event(ELOG_TYPE_RESET_BUTTON);
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}
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if (ps->gen_pmcon1 & GEN_RST_STS) {
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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}
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}
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static void log_wake_events(const struct chipset_power_state *ps)
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{
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const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS |
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PCIE_WAKE2_STS | PCIE_WAKE1_STS |
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PCIE_WAKE0_STS;
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uint32_t gpe0_sts;
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uint32_t gpio_mask;
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int i;
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/* Mask off disabled events. */
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gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
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if (ps->pm1_sts & WAK_STS) {
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
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acpi_is_wakeup_s3() ? 3 : 5);
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}
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if (ps->pm1_sts & PWRBTN_STS) {
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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}
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if (ps->pm1_sts & RTC_STS) {
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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}
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if (gpe0_sts & PME_B0_EN) {
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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}
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if (gpe0_sts & pcie_wake_mask) {
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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}
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gpio_mask = SUS_GPIO_STS0;
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i = 0;
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while (gpio_mask) {
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if (gpio_mask & gpe0_sts) {
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
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}
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gpio_mask <<= 1;
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i++;
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}
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}
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void southcluster_log_state(void)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL) {
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printk(BIOS_DEBUG, "Not logging power state information. "
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"Power state not found in cbmem.\n");
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return;
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}
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log_power_and_resets(ps);
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log_wake_events(ps);
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}
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