d2c57f2a0c
Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.
Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.
APL, even though it's younger than SPT, does not need mirroring.
Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
both the PCI cfg and DMI LGMR register get written correctly.
Tested successfully on clevo/cml-u.
Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/soc_chip.h>
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void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
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{
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const config_t *config = config_of_soc();
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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#if ENV_RAMSTAGE
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void lpc_soc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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pch_misc_init();
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/* Enable CLKRUN_EN for power gating ESPI */
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lpc_enable_pci_clk_cntl();
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/* Set ESPI Serial IRQ mode */
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if (CONFIG(SERIRQ_CONTINUOUS_MODE))
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lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
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else
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lpc_set_serirq_mode(SERIRQ_QUIET);
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/* Interrupt configuration */
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pch_enable_ioapic();
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pch_pirq_init();
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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}
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/* Fill up ESPI IO resource structure inside SoC directory */
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void pch_lpc_soc_fill_io_resources(struct device *dev)
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{
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/*
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* PMC pci device gets hidden from PCI bus due to Silicon
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* policy hence bind ACPI BASE aka ABASE (offset 0x20) with
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* ESPI IO resources to ensure that ABASE falls under PCI reserved
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* IO memory range.
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*
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* Note: Don't add any more resource with same offset 0x20
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* under this device space.
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*/
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pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
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ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
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}
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#endif
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