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Duncan Laurie f5e9ac48c6 SMM: Add support for malloc in SMM if using TSEG
This is used by the SPI driver and ELOG.

It requires SMM TSEG and a _heap/_eheap region defined in the
linker script.  The first time malloc is called in SMM the
start and end pointers to the heap region will be relocated
for the TSEG region.

Enable SPI flash and ELOG in SMM and successfully
allocate memory.  The allocated addresses are verified
to be sure they are within the TSEG heap region:

smm.elf:00014000 B _eheap
smm.elf:00010000 B _heap
TSEG base is 0xad000000

Memory allocated in ELOG:
ELOG: MEM @0xad018030

Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1312
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:44:19 +02:00
3rdparty@f933fda790 Finally update 3rdparty 2012-07-19 13:58:02 +02:00
documentation Whitespace/typo/cosmetic fixes (trivial). 2010-09-23 18:48:27 +00:00
payloads libpayload: Add reset function for OHCI USB driver 2012-07-12 10:00:17 +02:00
src SMM: Add support for malloc in SMM if using TSEG 2012-07-24 23:44:19 +02:00
util ifdtool: Use perror for file write errors 2012-07-24 10:13:33 +02:00
.gitignore romcc: kill gcc warnings and .gitignore generated files 2012-02-07 22:34:42 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Keep cscope.out when distclean. 2012-03-31 12:06:10 +02:00
Makefile.inc abuild: Build boards in parallel if possible 2012-05-10 22:11:16 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.