3e4e303858
coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2863 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/lynxpoint/gpio.h>
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#define GPIO_COUNT 6
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#define ACTIVE_LOW 0
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#define ACTIVE_HIGH 1
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return;
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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/* Write Protect: GPIO22 */
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gpios->gpios[0].port = 0;
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gpios->gpios[0].polarity = ACTIVE_LOW;
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gpios->gpios[0].value = (gp_lvl >> 22) & 1;
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strncpy((char *)gpios->gpios[0].name,"write protect",
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GPIO_MAX_NAME_LENGTH);
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/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
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gpios->gpios[1].port = 69;
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gpios->gpios[1].polarity = ACTIVE_HIGH;
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gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1;
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strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
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/* Developer: GPIO48 - BIOS_RESP - J8E4 (silkscreen: J8E3) */
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gpios->gpios[2].port = 48;
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gpios->gpios[2].polarity = ACTIVE_LOW;
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gpios->gpios[2].value = (gp_lvl2 >> (48-32)) & 1;
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strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
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/* Hard code the lid switch GPIO to open. */
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gpios->gpios[3].port = -1;
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gpios->gpios[3].polarity = ACTIVE_HIGH;
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gpios->gpios[3].value = 1;
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strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
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/* Power Button */
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gpios->gpios[4].port = -1;
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gpios->gpios[4].polarity = ACTIVE_HIGH;
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gpios->gpios[4].value = 0;
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strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
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/* Did we load the VGA option ROM? */
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gpios->gpios[5].port = -1;
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gpios->gpios[5].polarity = ACTIVE_HIGH;
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gpios->gpios[5].value = oprom_is_loaded;
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strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
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}
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#endif
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int get_developer_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
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/*
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* Developer: GPIO48, Connected to J8E4, however the silkscreen says
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* J8E3. The jumper is active low.
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*/
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return !((gp_lvl2 >> (48-32)) & 1);
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}
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int get_recovery_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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/*
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* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
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* J8E2. The jump is active high.
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*/
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return (gp_lvl3 >> (69-64)) & 1;
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}
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int get_write_protect_state(void)
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{
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return 0;
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}
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