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Jitao Shi f68cc81513 soc/mediatek: dsi: reduce the hbp and hfp for phy timing
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero,
hs_exit and the sof/eof of DSI packets, will enlarge the line time,
which causes the real frame on dsi bus to be lower than the one
calculated by video timing. Therefore, hfp_byte is reduced by d_phy to
compensate the increase in time by the extra data transfer. However, if
hfp_byte is not large enough, the hsync period will be increased on DSI
data, leading to display scrolling in firmware screen.

To avoid this situation, this patch changes the DSI Tx driver to reduce
both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp,
respectively. Refer to kernel's change in CL:1915442.

Also rename 'phy_timing' to 'timing' to sync with kernel upstream.

Since the phy timing initialization sequence has been corrected, the m
value adjustment in the analogix driver can be removed.

BUG=b:144824303
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
TEST=Boots and sees firmware screen on krane and juniper
TEST=No scrolling issue on juniper AUO and InnoLux panels

Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17 15:38:39 +00:00
3rdparty 3rdparty/blobs: Update to include STM binary 2020-02-05 18:50:48 +00:00
Documentation doc/tutorial/part1.md: Add commands for yum- & pacman-based distro 2020-02-12 18:45:31 +00:00
LICENSES LICENSES: Add licenses used in the coreboot repo 2019-10-30 08:23:51 +00:00
configs security/intel/stm: Add STM support 2020-02-05 18:49:27 +00:00
payloads libpayload: Make pci and endian handling -Wconversion safe 2020-02-05 21:48:36 +00:00
src soc/mediatek: dsi: reduce the hbp and hfp for phy timing 2020-02-17 15:38:39 +00:00
util crossgcc: Upgrade IASL to version 20200110 2020-02-12 19:48:58 +00:00
.checkpatch.conf
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Add pmh7tool binary 2019-11-27 09:05:55 +00:00
.gitmodules submodules: Add 3rdparty/amd_blobs 2019-10-31 12:28:38 +00:00
.gitreview
AUTHORS AUTHORS: add authors from src/superio 2020-01-30 12:00:23 +00:00
COPYING
MAINTAINERS commonlib: Add commonlib/bsd 2020-01-28 06:36:13 +00:00
Makefile util/kconfig: Move coreboot specific changes into Makefile.inc 2019-11-27 23:27:29 +00:00
Makefile.inc Makefile.inc: Adapt $(spc) definition 2020-02-12 21:20:12 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc
toolchain.inc Makefile: Remove romcc 2019-12-27 08:59:59 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.