159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
/*
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
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*
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* Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
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*/
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#include <stdint.h>
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#include <arch/cache.h>
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#include <arch/virtual.h>
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void tlb_invalidate_all(void)
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{
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/* TLBIALL includes dTLB and iTLB on systems that have them. */
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tlbiall();
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dsb();
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isb();
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}
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enum dcache_op {
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OP_DCCSW,
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OP_DCCISW,
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OP_DCISW,
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OP_DCCIMVAC,
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OP_DCCMVAC,
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OP_DCIMVAC,
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};
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unsigned int dcache_line_bytes(void)
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{
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uint32_t ccsidr;
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static unsigned int line_bytes = 0;
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if (line_bytes)
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return line_bytes;
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ccsidr = read_ccsidr();
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/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
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line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
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line_bytes *= sizeof(unsigned int); /* bytes per line */
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return line_bytes;
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}
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/*
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* Do a dcache operation by modified virtual address. This is useful for
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* maintaining coherency in drivers which do DMA transfers and only need to
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* perform cache maintenance on a particular memory range rather than the
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* entire cache.
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*/
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static void dcache_op_mva(void const *vaddr, size_t len, enum dcache_op op)
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{
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unsigned long line, linesize;
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unsigned long paddr = virt_to_phys(vaddr);
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linesize = dcache_line_bytes();
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line = paddr & ~(linesize - 1);
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dsb();
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while (line < paddr + len) {
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switch(op) {
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case OP_DCCIMVAC:
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dccimvac(line);
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break;
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case OP_DCCMVAC:
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dccmvac(line);
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break;
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case OP_DCIMVAC:
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dcimvac(line);
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break;
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default:
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break;
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}
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line += linesize;
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}
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isb();
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}
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void dcache_clean_by_mva(void const *addr, size_t len)
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{
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dcache_op_mva(addr, len, OP_DCCMVAC);
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}
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void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
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{
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dcache_op_mva(addr, len, OP_DCCIMVAC);
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}
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void dcache_invalidate_by_mva(void const *addr, size_t len)
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{
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dcache_op_mva(addr, len, OP_DCIMVAC);
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}
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/*
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* CAUTION: This implementation assumes that coreboot never uses non-identity
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* page tables for pages containing executed code. If you ever want to violate
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* this assumption, have fun figuring out the associated problems on your own.
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*/
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void dcache_mmu_disable(void)
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{
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uint32_t sctlr;
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dcache_clean_invalidate_all();
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sctlr = read_sctlr();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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write_sctlr(sctlr);
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}
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void dcache_mmu_enable(void)
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{
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uint32_t sctlr;
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sctlr = read_sctlr();
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sctlr |= SCTLR_C | SCTLR_M;
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write_sctlr(sctlr);
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}
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void cache_sync_instructions(void)
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{
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uint32_t sctlr;
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sctlr = read_sctlr();
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if (sctlr & SCTLR_C)
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dcache_clean_all();
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else if (sctlr & SCTLR_I)
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dcache_clean_invalidate_all();
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iciallu(); /* includes BPIALLU (architecturally) */
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dsb();
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isb();
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}
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