125 lines
3.2 KiB
ArmAsm
125 lines
3.2 KiB
ArmAsm
/*
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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.text
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.align 6
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.arm
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.global exception_table
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exception_table:
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b 1f
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b 2f
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b 3f
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b 4f
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b 5f
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b 6f
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b 7f
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b 8f
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1:
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mov sp, #0
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b exception_common
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/* Undefined Instruction (CAREFUL: the PC offset is specific to thumb mode!) */
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2:
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sub lr, lr, #2
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mov sp, #1
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b exception_common
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/* Software Interrupt (no PC offset necessary) */
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3:
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mov sp, #2
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b exception_common
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/* Prefetch Abort */
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4:
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sub lr, lr, #4
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mov sp, #3
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b exception_common
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/* Data Abort */
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5:
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sub lr, lr, #8
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mov sp, #4
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b exception_common
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/* (not used) */
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6:
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mov sp, #5
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b exception_common
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/* Interrupt */
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7:
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sub lr, lr, #4
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mov sp, #6
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b exception_common
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/* Fast Interrupt */
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8:
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sub lr, lr, #4
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mov sp, #7
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b exception_common
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exception_common:
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str sp, exception_idx
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ldr sp, exception_state_ptr
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stmia sp!, { r0 - r12 } /* Save regs from bottom to top */
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stmia sp, { sp, lr }^ /* Save banked SP/LR (no writeback) */
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str lr, [sp, #(4 * 2)] /* Save PC to ®s[13] + 2 */
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mrs r0, SPSR
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str r0, [sp, #(4 * 3)] /* Save SPSR to ®s[13] + 3 */
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ldr sp, exception_stack_end /* Point SP to the stack for C code */
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ldr r0, exception_idx
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blx exception_dispatch
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ldr sp, exception_state_ptr
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ldr r0, [sp, #(4 * 16)] /* Load SPSR from ®s[0] + 16... */
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msr SPSR_cxsf, r0 /* ...and get it out of the way */
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ldmia sp!, { r0 - r12 } /* Restore regs from bottom to top */
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ldmia sp, { sp, lr }^ /* Restore SP/LR to banked location */
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add sp, sp, #8 /* Adjust SP (no writeback allowed) */
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ldmia sp!, { pc }^ /* Do exception return (mode switch) */
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.align 2
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.global exception_stack_end
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exception_stack_end:
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.word 0
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.global exception_state_ptr
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exception_state_ptr:
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.word 0
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exception_idx:
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.word 0
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.thumb
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.global set_vbar
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.thumb_func
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set_vbar:
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mcr p15, 0, r0, c12, c0, 0
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bx lr
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