85f362e9b6
I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
568 lines
16 KiB
C
568 lines
16 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* ROMSIG At ROMBASE + 0x20000:
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* +------------+---------------+----------------+------------+
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* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
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* +------------+---------------+----------------+------------+
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* | PSPDIR ADDR|PSP2DIR ADDR |
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* +------------+---------------+
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* EC ROM should be 64K aligned.
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*
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* PSP directory (Where "PSPDIR ADDR" points)
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* +------------+---------------+----------------+------------+
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* | 'PSP$' | Fletcher | Count | Reserved |
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* +------------+---------------+----------------+------------+
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* | 0 | size | Base address | Reserved | Pubkey
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* +------------+---------------+----------------+------------+
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* | 1 | size | Base address | Reserved | Bootloader
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* +------------+---------------+----------------+------------+
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* | 8 | size | Base address | Reserved | Smu Firmware
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* +------------+---------------+----------------+------------+
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* | 3 | size | Base address | Reserved | Recovery Firmware
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* +------------+---------------+----------------+------------+
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* | |
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* | |
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* | Other PSP Firmware |
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* | |
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* | |
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* +------------+---------------+----------------+------------+
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*
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* PSP2 directory
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* +------------+---------------+----------------+------------+
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* | 'PSP2' | Fletcher | Count | Reserved |
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* +------------+---------------+----------------+------------+
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* | 1 | PSP ID | PSPDIR ADDR | | 2nd PSP directory
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* +------------+---------------+----------------+------------+
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* | 2 | PSP ID | PSPDIR ADDR | | 3rd PSP directory
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* +------------+---------------+----------------+------------+
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* | |
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* | Other PSP |
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* | |
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* +------------+---------------+----------------+------------+
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*
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*/
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#include <fcntl.h>
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#include <errno.h>
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#include <stdio.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <string.h>
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#include <stdlib.h>
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#include <getopt.h>
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#ifndef CONFIG_ROM_SIZE
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#define CONFIG_ROM_SIZE 0x400000
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#endif
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#define ROM_BASE_ADDRESS (0xFFFFFFFF - CONFIG_ROM_SIZE + 1)
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#define AMD_ROMSIG_OFFSET 0x20000
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#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1))
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/*
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Reserved for future.
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TODO: PSP2 is for Combo BIOS, which is the idea that one image supports 2
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kinds of APU.
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*/
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#define PSP2 1
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typedef unsigned int uint32_t;
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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/*
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* Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
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* The checksum field of the passed PDU does not need to be reset to zero.
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*
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* The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
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* Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
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* alternative to cyclical redundancy checks because it provides error-
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* detection properties similar to cyclical redundancy checks but at the
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* cost of a simple summation technique. Its characteristics were first
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* published in IEEE Transactions on Communications in January 1982. One
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* version has been adopted by ISO for use in the class-4 transport layer
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* of the network protocol.
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*
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* This program expects:
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* stdin: The input file to compute a checksum for. The input file
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* not be longer than 256 bytes.
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* stdout: Copied from the input file with the Fletcher's Checksum
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* inserted 8 bytes after the beginning of the file.
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* stderr: Used to print out error messages.
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*/
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uint32_t fletcher32 (const uint16_t *pptr, int length)
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{
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uint32_t c0;
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uint32_t c1;
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uint32_t checksum;
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int index;
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c0 = 0xFFFF;
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c1 = 0xFFFF;
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for (index = 0; index < length; index++) {
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/*
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* Ignore the contents of the checksum field.
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*/
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c0 += *(pptr++);
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c1 += c0;
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if ((index % 360) == 0) {
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c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow
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c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow
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}
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}
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c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow
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c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow
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checksum = (c1 << 16) | c0;
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return checksum;
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}
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void usage()
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{
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printf("Create AMD Firmware combination\n");
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}
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typedef enum _amd_fw_type {
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AMD_FW_PSP_PUBKEY = 0,
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AMD_FW_PSP_BOOTLOADER = 1,
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AMD_FW_PSP_SMU_FIRMWARE = 8,
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AMD_FW_PSP_RECOVERY = 3,
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AMD_FW_PSP_RTM_PUBKEY = 5,
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AMD_FW_PSP_SECURED_OS = 2,
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AMD_FW_PSP_NVRAM = 4,
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AMD_FW_PSP_SECURED_DEBUG = 9,
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AMD_FW_PSP_TRUSTLETS = 12,
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AMD_FW_PSP_TRUSTLETKEY = 13,
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AMD_FW_PSP_SMU_FIRMWARE2 = 18,
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AMD_PSP_FUSE_CHAIN = 11,
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AMD_FW_PSP_SMUSCS = 95,
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AMD_FW_IMC,
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AMD_FW_GEC,
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AMD_FW_XHCI,
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} amd_fw_type;
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typedef struct _amd_fw_entry {
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amd_fw_type type;
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char *filename;
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} amd_fw_entry;
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amd_fw_entry amd_psp_fw_table[] = {
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{ .type = AMD_FW_PSP_PUBKEY },
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{ .type = AMD_FW_PSP_BOOTLOADER },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE },
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{ .type = AMD_FW_PSP_RECOVERY },
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{ .type = AMD_FW_PSP_RTM_PUBKEY },
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{ .type = AMD_FW_PSP_SECURED_OS },
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{ .type = AMD_FW_PSP_NVRAM },
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{ .type = AMD_FW_PSP_SECURED_DEBUG },
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{ .type = AMD_FW_PSP_TRUSTLETS },
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{ .type = AMD_FW_PSP_TRUSTLETKEY },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2 },
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{ .type = AMD_FW_PSP_SMUSCS },
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{ .type = AMD_PSP_FUSE_CHAIN },
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};
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#if PSP2
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amd_fw_entry amd_psp2_fw_table[] = {
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{ .type = AMD_FW_PSP_PUBKEY },
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{ .type = AMD_FW_PSP_BOOTLOADER },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE },
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{ .type = AMD_FW_PSP_RECOVERY },
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{ .type = AMD_FW_PSP_RTM_PUBKEY },
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{ .type = AMD_FW_PSP_SECURED_OS },
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{ .type = AMD_FW_PSP_NVRAM },
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{ .type = AMD_FW_PSP_SECURED_DEBUG },
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{ .type = AMD_FW_PSP_TRUSTLETS },
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{ .type = AMD_FW_PSP_TRUSTLETKEY },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2 },
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{ .type = AMD_FW_PSP_SMUSCS },
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{ .type = AMD_PSP_FUSE_CHAIN },
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};
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#endif
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amd_fw_entry amd_fw_table[] = {
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{ .type = AMD_FW_XHCI },
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{ .type = AMD_FW_IMC },
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{ .type = AMD_FW_GEC },
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};
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void fill_psp_head(uint32_t *pspdir, int count)
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{
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pspdir[0] = 0x50535024; /* 'PSP$' */
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pspdir[2] = count; /* size */
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pspdir[3] = 0;
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pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2);
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}
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uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i)
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{
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int fd;
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struct stat fd_stat;
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if (amd_fw_table[i].filename != NULL) {
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fd = open (amd_fw_table[i].filename, O_RDONLY);
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fstat(fd, &fd_stat);
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switch (amd_fw_table[i].type) {
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case AMD_FW_IMC:
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pos = ALIGN(pos, 0x10000);
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romsig[1] = pos + ROM_BASE_ADDRESS;
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break;
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case AMD_FW_GEC:
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romsig[2] = pos + ROM_BASE_ADDRESS;
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break;
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case AMD_FW_XHCI:
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romsig[3] = pos + ROM_BASE_ADDRESS;
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break;
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default:
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/* Error */
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break;
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}
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read (fd, base+pos, fd_stat.st_size);
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pos += fd_stat.st_size;
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pos = ALIGN(pos, 0x100);
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close (fd);
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}
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return pos;
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}
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uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i)
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{
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int fd;
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struct stat fd_stat;
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if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
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pspdir[4+4*i+0] = amd_psp_fw_table[i].type;
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pspdir[4+4*i+1] = 0xFFFFFFFF;
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pspdir[4+4*i+2] = 1;
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pspdir[4+4*i+3] = 0;
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} else if (amd_psp_fw_table[i].filename != NULL) {
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pspdir[4+4*i+0] = amd_psp_fw_table[i].type;
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fd = open (amd_psp_fw_table[i].filename, O_RDONLY);
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fstat(fd, &fd_stat);
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pspdir[4+4*i+1] = fd_stat.st_size;
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pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS;
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pspdir[4+4*i+3] = 0;
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read (fd, base+pos, fd_stat.st_size);
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pos += fd_stat.st_size;
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pos = ALIGN(pos, 0x100);
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close (fd);
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} else {
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/* This APU doesn't have this firmware. */
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}
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return pos;
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}
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static const char *optstring = "x:i:g:p:b:s:r:k:o:n:d:t:u:w:m:h";
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static struct option long_options[] = {
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{"xhci", required_argument, 0, 'x' },
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{"imc", required_argument, 0, 'i' },
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{"gec", required_argument, 0, 'g' },
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/* PSP */
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{"pubkey", required_argument, 0, 'p' },
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{"bootloader", required_argument, 0, 'b' },
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{"smufirmware", required_argument, 0, 's' },
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{"recovery", required_argument, 0, 'r' },
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{"rtmpubkey", required_argument, 0, 'k' },
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{"secureos", required_argument, 0, 'c' },
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{"nvram", required_argument, 0, 'n' },
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{"securedebug", required_argument, 0, 'd' },
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{"trustlets", required_argument, 0, 't' },
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{"trustletkey", required_argument, 0, 'u' },
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{"smufirmware2", required_argument, 0, 'w' },
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{"smuscs", required_argument, 0, 'm' },
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/* TODO: PSP2 */
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#if PSP2
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{"pubkey2", required_argument, 0, 'P' },
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{"bootloader2", required_argument, 0, 'B' },
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{"smufirmware2", required_argument, 0, 'S' },
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{"recovery2", required_argument, 0, 'R' },
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{"rtmpubkey2", required_argument, 0, 'K' },
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{"secureos2", required_argument, 0, 'C' },
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{"nvram2", required_argument, 0, 'N' },
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{"securedebug2", required_argument, 0, 'D' },
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{"trustlets2", required_argument, 0, 'T' },
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{"trustletkey2", required_argument, 0, 'U' },
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{"smufirmware2_2",required_argument, 0, 'W' },
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{"smuscs2", required_argument, 0, 'M' },
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#endif
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{"output", required_argument, 0, 'o' },
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{"help", no_argument, 0, 'h' },
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{NULL, 0, 0, 0 }
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};
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void register_fw_filename(amd_fw_type type, char filename[], int pspflag)
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{
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int i;
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for (i = 0; i < sizeof(amd_fw_table)/sizeof(amd_fw_entry); i++) {
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if (amd_fw_table[i].type == type) {
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amd_fw_table[i].filename = filename;
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return;
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}
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}
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if (pspflag == 1) {
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for (i = 0; i < sizeof(amd_psp_fw_table)/sizeof(amd_fw_entry); i++) {
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if (amd_psp_fw_table[i].type == type) {
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amd_psp_fw_table[i].filename = filename;
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return;
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}
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}
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}
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#if PSP2
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if (pspflag == 2) {
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for (i = 0; i < sizeof(amd_psp2_fw_table)/sizeof(amd_fw_entry); i++) {
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if (amd_psp2_fw_table[i].type == type) {
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amd_psp2_fw_table[i].filename = filename;
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return;
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}
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}
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}
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#endif
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}
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int main(int argc, char **argv)
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{
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int c, count, pspflag = 0;
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#if PSP2
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int psp2flag = 0;
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int psp2count;
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uint32_t *psp2dir;
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#endif
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void *rom = NULL;
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uint32_t current;
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uint32_t *amd_romsig, *pspdir;
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int targetfd;
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char *output;
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rom = malloc(CONFIG_ROM_SIZE);
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memset (rom, 0xFF, CONFIG_ROM_SIZE);
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if (!rom) {
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return 1;
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}
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current = AMD_ROMSIG_OFFSET;
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amd_romsig = rom + AMD_ROMSIG_OFFSET;
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amd_romsig[0] = 0x55AA55AA; /* romsig */
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amd_romsig[1] = 0;
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amd_romsig[2] = 0;
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amd_romsig[3] = 0;
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current += 0x20; /* size of ROMSIG */
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while (1) {
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int optindex = 0;
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c = getopt_long(argc, argv, optstring, long_options, &optindex);
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if (c == -1)
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break;
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switch (c) {
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case 'x':
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register_fw_filename(AMD_FW_XHCI, optarg, 0);
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break;
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case 'i':
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register_fw_filename(AMD_FW_IMC, optarg, 0);
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break;
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case 'g':
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register_fw_filename(AMD_FW_GEC, optarg, 0);
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break;
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case 'p':
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register_fw_filename(AMD_FW_PSP_PUBKEY, optarg, 1);
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pspflag = 1;
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break;
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case 'b':
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register_fw_filename(AMD_FW_PSP_BOOTLOADER, optarg, 1);
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pspflag = 1;
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break;
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case 's':
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register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, optarg, 1);
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pspflag = 1;
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break;
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case 'r':
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register_fw_filename(AMD_FW_PSP_RECOVERY, optarg, 1);
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pspflag = 1;
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break;
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case 'k':
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register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, optarg, 1);
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pspflag = 1;
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break;
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case 'c':
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register_fw_filename(AMD_FW_PSP_SECURED_OS, optarg, 1);
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pspflag = 1;
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break;
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case 'n':
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register_fw_filename(AMD_FW_PSP_NVRAM, optarg, 1);
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pspflag = 1;
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break;
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case 'd':
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register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, optarg, 1);
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pspflag = 1;
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break;
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case 't':
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register_fw_filename(AMD_FW_PSP_TRUSTLETS, optarg, 1);
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pspflag = 1;
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break;
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case 'u':
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register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, optarg, 1);
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pspflag = 1;
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break;
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case 'w':
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register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, optarg, 1);
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pspflag = 1;
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break;
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case 'm':
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register_fw_filename(AMD_FW_PSP_SMUSCS, optarg, 1);
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pspflag = 1;
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break;
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#if PSP2
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case 'P':
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register_fw_filename(AMD_FW_PSP_PUBKEY, optarg, 2);
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psp2flag = 1;
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break;
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case 'B':
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register_fw_filename(AMD_FW_PSP_BOOTLOADER, optarg, 2);
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psp2flag = 1;
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break;
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case 'S':
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register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, optarg, 2);
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psp2flag = 1;
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break;
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case 'R':
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register_fw_filename(AMD_FW_PSP_RECOVERY, optarg, 2);
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psp2flag = 1;
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break;
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case 'K':
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register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, optarg, 2);
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|
psp2flag = 1;
|
|
break;
|
|
case 'C':
|
|
register_fw_filename(AMD_FW_PSP_SECURED_OS, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'N':
|
|
register_fw_filename(AMD_FW_PSP_NVRAM, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'D':
|
|
register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'T':
|
|
register_fw_filename(AMD_FW_PSP_TRUSTLETS, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'U':
|
|
register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'W':
|
|
register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
case 'M':
|
|
register_fw_filename(AMD_FW_PSP_SMUSCS, optarg, 2);
|
|
psp2flag = 1;
|
|
break;
|
|
#endif
|
|
case 'o':
|
|
output = optarg;
|
|
break;
|
|
case 'h':
|
|
usage();
|
|
return 1;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
current = ALIGN(current, 0x100);
|
|
for (count = 0; count < sizeof(amd_fw_table) / sizeof(amd_fw_entry); count ++) {
|
|
current = integerate_one_fw(rom, current, amd_romsig, count);
|
|
}
|
|
|
|
if (pspflag == 1) {
|
|
current = ALIGN(current, 0x10000);
|
|
pspdir = rom + current;
|
|
amd_romsig[4] = current + ROM_BASE_ADDRESS;
|
|
|
|
current += 0x200; /* Conservative size of pspdir */
|
|
for (count = 0; count < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); count ++) {
|
|
current = integerate_one_psp(rom, current, pspdir, count);
|
|
}
|
|
|
|
fill_psp_head(pspdir, count);
|
|
|
|
#if PSP2
|
|
if (psp2flag == 1) {
|
|
current = ALIGN(current, 0x10000); /* PSP2 dir */
|
|
psp2dir = rom + current;
|
|
amd_romsig[5] = current + ROM_BASE_ADDRESS;
|
|
current += 0x100; /* Add conservative size of psp2dir. */
|
|
|
|
/* TODO: remove the hardcode. */
|
|
psp2count = 1; /* Start from 1. */
|
|
/* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */
|
|
psp2dir[psp2count*4 + 0] = psp2count; /* PSP Number */
|
|
psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */
|
|
psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS;
|
|
pspdir = rom + current;
|
|
psp2dir[psp2count*4 + 3] = 0;
|
|
|
|
current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */
|
|
for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) {
|
|
current = integerate_one_psp(rom, current, pspdir, count);
|
|
}
|
|
fill_psp_head(pspdir, count);
|
|
/* } */ /* End of loop */
|
|
|
|
/* fill the PSP2 head */
|
|
psp2dir[0] = 0x50535032; /* 'PSP2' */
|
|
psp2dir[2] = psp2count; /* Count */
|
|
psp2dir[3] = 0;
|
|
psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
|
|
write(targetfd, amd_romsig, current - AMD_ROMSIG_OFFSET);
|
|
close(targetfd);
|
|
free(rom);
|
|
|
|
return 0;
|
|
}
|