coreboot-kgpe-d16/src
Karthikeyan Ramasubramanian f752fc6546 mb/google/sarien: Configure IRQs as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-22 22:17:07 +00:00
..
acpi ACPI: Define acpi_get_preferred_pm_profile() 2020-11-19 22:58:41 +00:00
arch ACPI S3: Split arch-agnostic parts 2020-11-19 22:58:11 +00:00
commonlib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
console console: Override uart base address 2020-11-09 07:46:10 +00:00
cpu intel/socket_441: Increase bootblock size 2020-11-21 01:53:18 +00:00
device device/pci: Add NULL check for PCI driver's .ops 2020-11-16 12:15:38 +00:00
drivers intel/fsp2_0: Add soc_validate_fsp_version for FSP version check 2020-11-20 18:58:54 +00:00
ec ec/google/chromeec: Add more wrappers for regulator control 2020-11-18 06:13:12 +00:00
include cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
lib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
mainboard mb/google/sarien: Configure IRQs as level triggered for HID over I2C 2020-11-22 22:17:07 +00:00
northbridge nb/intel/sandybridge: Clean up COMPOFST1 logic 2020-11-22 22:14:03 +00:00
security cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
soc soc/amd: move non-CAR linker scripts to common directory 2020-11-22 17:35:20 +00:00
southbridge sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs 2020-11-22 14:25:30 +00:00
superio superio/smsc/sio1036: Support 16-bit IO port addressing 2020-11-18 13:12:11 +00:00
vendorcode vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS 2020-11-22 22:15:07 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00