cd92979d44
Change-Id: I8e36dc1553faa618aa852c06861029b4c0bdb27a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
150 lines
4 KiB
Text
150 lines
4 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i945
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# IGD Displays
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register "gfx.ndid" = "2"
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register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }"
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device cpu_cluster 0 on
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chip cpu/intel/socket_m
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device lapic 0 on end
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end
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end
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register "pci_mmio_size" = "768"
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 01.0 off end # i945 PCIe root port
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device pci 02.0 on end # vga controller
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device pci 02.1 on end # display controller
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0a"
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register "pirqb_routing" = "0x0a"
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register "pirqc_routing" = "0x0a"
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register "pirqd_routing" = "0x0a"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x0a"
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register "pirqh_routing" = "0x0a"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi8_routing" = "1" # EXTSMI low active
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register "gpi7_routing" = "2" # ECSCI low active
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# GPE0 Enables
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register "gpe0_en" = "0x00800106"
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register "alt_gp_smi_en" = "0x0100"
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register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "c3_latency" = "85"
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register "docking_supported" = "1"
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register "p_cnt_throttling_supported" = "1"
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe port 1
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device pci 1c.1 on end # PCIe port 2
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device pci 1c.2 on end # PCIe port 3
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device pci 1c.3 on end # PCIe port 4
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device pci 1c.4 off end # PCIe port 5
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device pci 1c.5 off end # PCIe port 6
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device pci 1d.0 on end # USB UHCI
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device pci 1d.1 on end # USB UHCI
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device pci 1d.2 on end # USB UHCI
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device pci 1d.3 on end # USB UHCI
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device pci 1d.7 on end # USB2 EHCI
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device pci 1e.0 on
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chip southbridge/ti/pcixx12
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end
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end # PCI bridge
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device pci 1e.2 off end # AC'97 Audio
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device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/fdc37n972
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device pnp 2e.0 off # Floppy
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end
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device pnp 2e.1 off # ACPI PM
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end
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# 2e.2 does not exist
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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end
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device pnp 2e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off
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end
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#device pnp 2e.6 on # RTC
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# io 0x60 = 0x70
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# io 0x62 = 0x74
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#end
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device pnp 2e.7 off # Keyboard
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end
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device pnp 2e.8 off # EC
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io 0x60 = 0x62
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end
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#device pnp 2e.9 on # Mailbox
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#end
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end
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chip superio/smsc/sio10n268
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device pnp 4e.0 off # Floppy
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end
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device pnp 4e.1 off # Parport
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end
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#device pnp 4e.2 on # COM3
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# io 0x60 = 0x3e8
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# irq 0x70 = 6
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#end
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#device pnp 4e.3 on # COM4
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# io 0x60 = 0x2e8
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# irq 0x70 = 6
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#end
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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end
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device pnp 4e.7 off # GPIO1, GAME, MIDI
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end
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device pnp 4e.8 off # GPIO2
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end
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device pnp 4e.9 off # GPIO3/4
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end
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device pnp 4e.a off # ACPI
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end
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device pnp 4e.b off # HWM
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end
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chip ec/acpi
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end
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end
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end
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device pci 1f.1 off end # IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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end
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end
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end
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