coreboot-kgpe-d16/src/soc
Lijian Zhao f7bcc180eb soc/intel/common: Add Cannonlake PCI id
Add extra pci ids of CNLU and CNLY into common code.

Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27 16:02:49 +00:00
..
amd amd/stoneyridge: Convert MP init to mp_init_with_smm 2017-09-27 15:56:55 +00:00
broadcom/cygnus mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
dmp/vortex86ex
imgtec/pistachio mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
intel soc/intel/common: Add Cannonlake PCI id 2017-09-27 16:02:49 +00:00
lowrisc/lowrisc
marvell/mvmap2315
mediatek/mt8173 mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
nvidia mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
qualcomm mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
rockchip include/device: Split i2c.h into three 2017-08-18 15:33:29 +00:00
samsung mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
ucb/riscv