a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
265 lines
7.2 KiB
Text
265 lines
7.2 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
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{
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#include "northbridge/amd/amdk8/util.asl"
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/* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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* Any others would involve declaring the wake up methods.
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*/
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
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Name (PICM, 0x00)
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Method (_PIC, 1, Serialized) {
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Store (Arg0, PICM)
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}
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top PCI device (CK804) */
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Device (PCI0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00)
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Name (_UID, 0x00)
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Name (_BBN, 0x00)
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0CF8, // Address Length
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,, , TypeStatic)
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})
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/* Methods bellow use SSDT to get actual MMIO regs
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The IO ports are from 0xd00, optionally an VGA,
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otherwise the info from MMIO is used.
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\_SB.GXXX(node, link)
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*/
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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#include "southbridge/nvidia/ck804/acpi/ck804.asl"
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/* PCI Routing Table */
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Name (_PRT, Package () {
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Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },//APCS
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Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },//APCS
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Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },//APCF
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Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },//APCL
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Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },//APCJ
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Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },//APCK
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Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },//APCZ
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Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },//APSI
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Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },//APSJ
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Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
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Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },//APCH
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Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },//APC2
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})
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Device (PCIC)
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{
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Name (_ADR, 0x00090000)
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Name (_UID, 0x00)
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Name (_PRT, Package () {
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/* AGR slot */
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
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})
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}
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/* 2:00 PCIe x1 */
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Device (PEX1)
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{
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Name (_ADR, 0x000d0000)
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Name (_UID, 0x00)
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}
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/* 3:00 PCIe x16 */
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Device (PEX0)
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{
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Name (_ADR, 0x000e0000)
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Name (_UID, 0x00)
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}
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Device (LPC) {
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00010000)
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OperationRegion (CF44, PCI_Config, 0x44, 0x04)
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Field (CF44, ByteAcc, NoLock, Preserve)
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{
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ETBA, 32,
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}
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/* PS/2 keyboard (seems to be important for WinXP install) */
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Device (KBD)
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{
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Name (_HID, EisaId ("PNP0303"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
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IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Return (TMP)
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}
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}
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/* PS/2 mouse */
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Device (MOU)
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{
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Name (_HID, EisaId ("PNP0F13"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IRQNoFlags () {12}
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})
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Return (TMP)
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}
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}
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/* Parallel port */
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Device (LP0)
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{
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Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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FixedIO (0x0378, 0x10)
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IRQNoFlags () {7}
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})
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Return (TMP)
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}
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}
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/* Floppy controller */
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Device (FDC0)
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{
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Name (_HID, EisaId ("PNP0700"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () {
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FixedIO (0x03F0, 0x08)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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Return (BUF0)
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}
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}
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#if 0
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Device (HPET)
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{
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Name (_HID, EisaId ("PNP0103"))
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Name (CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly,
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0x00000000,
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0x00001000,
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_Y02)
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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Method (_CRS, 0, NotSerialized)
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{
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CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
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Store (ETBA, HPT)
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Return (CRS)
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}
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}
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#endif
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}
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}
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}
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}
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