a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern u8 bus_rs780[11];
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extern u8 bus_sb700[2];
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extern u32 apicid_sb700;
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extern u32 sbdn_rs780;
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extern u32 sbdn_sb700;
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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get_bus_conf();
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address */
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{
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device_t dev;
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u32 dword;
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u8 byte;
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dev =
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dev_find_slot(bus_sb700[0],
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PCI_DEVFN(sbdn_sb700 + 0x14, 0));
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if (dev) {
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dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
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smp_write_ioapic(mc, apicid_sb700,
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0x11,(void *) dword);
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/* Initialize interrupt mapping */
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/* aza */
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byte = pci_read_config8(dev, 0x63);
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byte &= 0xf8;
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byte |= 0; /* 0: INTA, ...., 7: INTH */
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pci_write_config8(dev, 0x63, byte);
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/* SATA */
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dword = pci_read_config32(dev, 0xac);
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dword &= ~(7 << 26);
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dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
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/* dword |= 1<<22; PIC and APIC co exists */
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pci_write_config32(dev, 0xac, dword);
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/*
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* 00:12.0: PROG SATA : INT F
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* 00:13.0: INTA USB_0
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* 00:13.1: INTB USB_1
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* 00:13.2: INTC USB_2
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* 00:13.3: INTD USB_3
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* 00:13.4: INTC USB_4
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* 00:13.5: INTD USB2
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* 00:14.1: INTA IDE
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* 00:14.2: Prog HDA : INT E
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* 00:14.5: INTB ACI
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* 00:14.6: INTB MCI
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*/
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}
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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