cad9e7a6ec
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/io.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/clk_rst.h>
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#include <soc/ccplex.h>
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#include <soc/cpu.h>
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#include <soc/flow.h>
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#include <soc/mc.h>
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#include <soc/pmc.h>
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#include <soc/power.h>
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#include <soc/romstage.h>
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#include <string.h>
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#include <timer.h>
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#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
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static void enable_cpu_clocks(void)
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{
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clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE |
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SET_CLK_ENB_CPULP_ENABLE, 0, 0, 0);
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}
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static void enable_cpu_power_partitions(void)
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{
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/* Bring up fast cluster, non-CPU, CPU0, CPU1, CPU2 and CPU3 parts. */
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power_ungate_partition(POWER_PARTID_CRAIL);
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power_ungate_partition(POWER_PARTID_C0NC);
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power_ungate_partition(POWER_PARTID_CE0);
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if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) {
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power_ungate_partition(POWER_PARTID_CE1);
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power_ungate_partition(POWER_PARTID_CE2);
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power_ungate_partition(POWER_PARTID_CE3);
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}
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if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
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/*
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* Deassert reset signal of all the secondary CPUs.
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* PMC and flow controller will take over the power sequence
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* controller in the ATF.
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*/
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uint32_t reg = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
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CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CX1 |
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CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_DBG2 |
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CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CX2 |
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CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG3 |
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CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3;
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write32(CLK_RST_REG(rst_cpug_cmplx_clr), reg);
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}
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}
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static void request_ram_repair(void)
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{
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struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE;
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const uint32_t req = 1 << 0;
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const uint32_t sts = 1 << 1;
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uint32_t reg;
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struct stopwatch sw;
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printk(BIOS_DEBUG, "Requesting RAM repair.\n");
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stopwatch_init(&sw);
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/* Perform ram repair */
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reg = read32(&flow->ram_repair);
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reg |= req;
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write32(&flow->ram_repair, reg);
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while ((read32(&flow->ram_repair) & sts) != sts)
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;
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printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n",
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stopwatch_duration_usecs(&sw));
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}
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static void set_cpu_ack_width(uint32_t val)
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{
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uint32_t reg;
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reg = read32(CLK_RST_REG(cpu_softrst_ctrl2));
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reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
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reg |= val;
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write32(CLK_RST_REG(cpu_softrst_ctrl2), reg);
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}
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void ccplex_cpu_prepare(void)
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{
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enable_cpu_clocks();
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/*
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* The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200.
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* The recommended value is 0.
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*/
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set_cpu_ack_width(0);
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enable_cpu_power_partitions();
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mainboard_configure_pmc();
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mainboard_enable_vdd_cpu();
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request_ram_repair();
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}
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static void start_common_clocks(void)
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{
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/* Clear fast CPU partition reset. */
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write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU);
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/* Clear reset of L2 and CoreSight components. */
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write32(CLK_RST_REG(rst_cpug_cmplx_clr),
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CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
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}
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void ccplex_cpu_start(void *entry_addr)
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{
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/* Enable common clocks for the shared resources between the cores. */
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start_common_clocks();
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start_cpu(0, entry_addr);
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}
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